Resonance in Electrical Circuits

A couple of days ago, I was reviewing a client’s design and noticed something interesting. Every IC power pin had between four and six capacitors: 10 µF, 1 µF, 0.1 µF, 33 pF, and 10 pF. A full “capacitor zoo” replicated across the board. At first glance, it looks thorough. The intent is to “cover every frequency range”. This is where physics steps in. Each capacitor introduces parasitic inductance and resistance. When many values are placed in parallel, the network forms multiple LC tank resonances that interact with each other. Instead of flattening the impedance, these LC tanks can create peaks at certain frequencies, increasing ripple and ringing on the power rail. Often, a well sized bulk capacitor for low frequency energy storage combined with a single properly selected decoupling capacitor for the relevant high frequency range is sufficient, provided placement and return paths are correct. #HardwareDesign #EMI #PowerIntegrity #Resonance #Decoupling #PCBDesign

We’re often told to place decoupling capacitors as close to the IC as possible. But in high-speed design, that advice is an oversimplification. At high frequencies (f), what really matters is the impedance (Z) seen by noise 🔊. ⚡️ And this impedance isn’t determined by resistance 🚧. It’s dominated by the total inductance (Lloop) of the current path 🛣️ and the relationship is straightforward, Z ≈ jωLloop (where ω=2πf) This total loop inductance sets the capacitor’s self-resonant frequency (SRF), the point where it’s most effective. Once you go above its SRF, the capacitor starts behaving like an inductor, making it useless for suppressing high-frequency noise. To effectively tackle high-frequency noise, you need to minimize impedance by reducing the total loop inductance, which consists of, Lloop=Ltrace+Lcap_ESL+Lvia Focusing only on shortening the trace (L_trace) by a few millimeters often overlooks the bigger culprit: L_via ❌. The real objective is to shrink the entire loop area, which typically means prioritizing via placement 📌 to ensure the most direct connection 🛣️ to the ground plane 🟦. A well-placed via can be more critical than simply placing the capacitor physically close to the IC. ✅ The correct approach: First, determine the optimal via positions to create the shortest, most direct path from the capacitor pads to the power and ground planes. Then, place the capacitor in that optimal spot as close as practical to the IC power pins to keep the total loop inductance as low as possible. And don't Forget the Capacitor ESL. 🎯 Stop thinking in millimeters 📏. Start designing in nanohenries 🔬. #PowerIntegrity #SignalIntegrity #CircuitDesign #PCBDesign #HighSpeedDesign #EMC #EMI #ElectronicEngineering

Unexpected Resonances – EMI Filters vs. Converter Control Loops: Sometimes the hardest problems in power electronics aren’t inside the converter itself, but in how it interacts with its environment. A classic example: resonances between EMI filters and converter control loops. The issue: *EMI filters add extra poles and zeros into the system. If the converter’s control loop isn’t designed with this in mind, their interaction can create unexpected resonances. *The result? Oscillations, instability, failed compliance tests, or strange field failures that are hard to reproduce. How to predict and damp: *Model the input impedance of the converter and the output impedance of the EMI filter – instability often arises when the two are comparable. *Use Middlebrook’s criterion as a design guideline. *Add damping networks (RC snubbers, resistive damping in filter capacitors, or active damping). *Validate with frequency response analysis (FRA), not just time-domain testing. Lesson learned: An EMI filter is not just an add-on for compliance – it becomes part of the control system. Treating it as such early in design saves painful debugging later.

The Sallen-Key low-pass filter shown here is a widely used second-order active filter topology in analog signal processing. It employs an operational amplifier configured as a voltage follower, along with two resistors and two capacitors, to realize a low-pass frequency response with controllable cutoff frequency and quality factor Q. The circuit passes low-frequency signals with minimal attenuation while progressively attenuating higher frequencies beyond the cutoff. The frequency-response plot correctly illustrates how the magnitude response changes with different Q values. Lower Q values such as 0.5 result in an overdamped response with a smooth roll-off and no peaking. A Q of 0.707 corresponds to a Butterworth response, which provides a maximally flat passband. As Q increases above 1, resonance appears near the cutoff frequency, producing noticeable gain peaking. Very high Q values, such as 5 or 10, show sharp resonance and ringing behavior. This visualization accurately represents practical filter behavior and is suitable for educational and design reference purposes in audio, instrumentation, and signal-conditioning applications.

Harmonics are inevitable, but harmonic mitigation is still essential and here’s what manufacturers never tell you. In every modern industrial plant, offshore platforms, water injection pumps, compressors, HVAC, data centers, harmonics are no longer the exception. They are the rule. Every diode, SCR, rectifier, UPS, charger and PWM inverter produces harmonics simply because of the way power electronics work. So a common question is: If harmonics are inevitable, why do we even bother with filters? And why do manufacturers never talk about the real harmonic issues? Let’s address both clearly. 1) Harmonic generation is inevitable Every power converter injects harmonic current Ih. The issue is how the network impedance reacts at those frequencies. The impedance of the network changes with frequency: Z(ω) = R + j·ω·L − j/(ω·C) • At some harmonic frequencies, Z(ω) becomes very high: voltage distortion increases. • At some frequencies, Z(ω) becomes very low: resonance occurs. • Both conditions amplify harmonics even if the source current stays the same. Filtering reshapes Z(ω) so the system does not amplify harmonic distortion but: • Filtering does not remove harmonics at the drive. • It removes the network’s vulnerability to them. 2) Filtering protects equipment, even if harmonics still flow Transformer stray losses increase with harmonic order: P_loss ≈ Σ (Ih² × h²) So filtering reduces high-order components that overheat transformers. Harmonics still exist, but their damage disappears. Why manufacturers hide the real harmonic picture? This is the part rarely mentioned openly. A) They only show harmonics up to the 50th order because above the 50th you find: • switching spikes • interharmonics • notching • 2–30 kHz emissions • high-frequency stress that damages LCL filters and capacitor banks Therefore, showing the full spectrum would scare customers. B) They test their equipment in perfect laboratory conditions and datasheets show THD at: • 100% load • balanced voltage • zero background distortion • strong grid • no capacitor banks present Real plants operate between 10–90% load and with existing distortion. Harmonics increase sharply in real conditions. C) They avoid talking about resonance Every system has a resonant frequency: f_res = 1 / (2π × √(L × C)) but manufacturers rarely mention: • how their drive interacts with the site L and C • how capacitor banks shift the resonance • how subsea cables add capacitance • how transformers saturate at dips Admitting this immediately forces the customer to buy filters and reactors which increasing cost and reducing sales. Conclusion: To build reliable plants we must: • measure the full spectrum (not just to 50th order). • scan impedance and resonance. • design filters for real operating conditions. • consider dynamics like motor starting, transformer energization, PoW switching, and long cables. Harmonics are inevitable. Harmonic damage is not. #powersystemsengineering

When you look at VDS in a #SiC switching cell, you’re not just looking at a waveform. You’re looking at the parasitic DNA of your #PowerElectronics power stage. Double Pulse Test results — 800 V DC bus, 120 A peak current. First run with Rg = 0 Ω, second run with Rg = 2.2 Ω. With Rg = 0 Ω, the device is switching at full capability. The measured dv/dt reached ~32 V/ns. As expected, we observed ~100 V overshoot and a high-frequency ringing at ~79.5 MHz with ~100 V amplitude. That 79.5 MHz number is important. High ringing frequency means very low commutation loop inductance. In other words, the layout is tight. The LC tank formed by loop inductance and MOSFET Coss is small. This is exactly what we aim for in an 800 V SiC design. The ringing itself is not instability. It is the natural resonance between: • Power loop inductance • Device output capacitance • Parasitic layout capacitances At Rg = 0 Ω, the current transition is extremely fast, injecting maximum energy into that LC network. Result: higher ringing amplitude. Now increase Rg to 2.2 Ω. The resonance frequency remains essentially unchanged (because L and C didn’t change), but the amplitude drops from ~100 V to ~65 V. Why? Because we reduced the excitation energy — not the parasitics themselves. This is a key distinction. You don’t “remove” ringing by slowing the device blindly. You control how hard you excite the existing parasitic network. A second resonance at ~422 kHz with ~25 V amplitude is also visible — classic DC-link bus inductance interacting with bulk capacitance. Different loop. Different physics. Completely predictable. What this test confirms: • The commutation loop inductance is very low (80 MHz is strong evidence). • The switching cell is behaving exactly as physics predicts. • Gate resistance directly controls excitation energy, not resonance frequency. SiC at 800 V / 120 A will always reveal your parasitics — beautifully and honestly. This is why double pulse testing remains the most powerful diagnostic tool in #WideBandgap design. The waveform doesn’t lie. Curious to hear how others tune gate resistance versus snubber strategy in high-voltage SiC platforms. #DoublePulseTest #InverterDesign #GateDriver #PCBLayout

𝐒𝐞𝐜𝐨𝐧𝐝-𝐎𝐫𝐝𝐞𝐫 𝐂𝐢𝐫𝐜𝐮𝐢𝐭𝐬 𝟏𝟎𝟏 & 𝐌𝐚𝐬𝐬 𝐒𝐩𝐞𝐜𝐭𝐫𝐨𝐦𝐞𝐭𝐫𝐲 𝐃𝐞𝐭𝐞𝐜𝐭𝐨𝐫𝐬 RLC circuits: the stuff of engineering nightmares.  Oscillations, damping ratios, resonance… concepts often assumed to be left behind in Circuit Analysis II. Surprise! They're running the show in your Orbitrap and TOF detectors right now. 𝐖𝐡𝐚𝐭 𝐢𝐬 𝐚 𝐬𝐞𝐜𝐨𝐧𝐝-𝐨𝐫𝐝𝐞𝐫 𝐜𝐢𝐫𝐜𝐮𝐢𝐭? 𝐒𝐭𝐫𝐚𝐧𝐠𝐞, 𝐫𝐢𝐠𝐡𝐭? 𝐀𝐧𝐝 𝐰𝐡𝐚𝐭 𝐝𝐨𝐞𝐬 𝐑𝐋𝐂 𝐞𝐯𝐞𝐧 𝐦𝐞𝐚𝐧? 𝐍𝐨𝐭 𝐬𝐭𝐫𝐚𝐧𝐠𝐞 𝐚𝐭 𝐚𝐥𝐥. 𝐈𝐭’𝐬 𝐭𝐡𝐞 𝐚𝐥𝐩𝐡𝐚𝐛𝐞𝐭 𝐨𝐟 𝐡𝐨𝐰 𝐬𝐢𝐠𝐧𝐚𝐥𝐬 𝐛𝐞𝐡𝐚𝐯𝐞: R (Resistor) → energy loss — your damping dial L (Inductor) → resists current changes — the system's inertia C (Capacitor) → resists voltage changes — the system's memory Together they form a circuit that can oscillate, ring, or settle smoothly. Change R, L or C → you change rise time, ringing, lifetime and baseline. ⭐𝐎𝐫𝐛𝐢𝐭𝐫𝐚𝐩: 𝐀 𝐇𝐢𝐠𝐡-𝐐 𝐇𝐚𝐫𝐦𝐨𝐧𝐢𝐜 𝐎𝐬𝐜𝐢𝐥𝐥𝐚𝐭𝐨𝐫 Ions in an Orbitrap move in a near-harmonic potential: m·d²z/dt² + k·z = 0 Each m/z gives a precise oscillation frequency (∝ √q/m) and induces an image current on the outer electrodes, read by a high-impedance, ultra-low-noise preamplifier. Trap + wiring + preamp behave like an RLC network: Too little damping → ringing, baseline drift Too much → transient dies fast, resolution drops So the electronics are tuned near critical damping for injection, while ion motion itself is kept lightly damped (high Q) so oscillations survive for hundreds of ms. 👉 Orbitrap = a high-Q second-order resonator in both 𝐢𝐨𝐧 𝐝𝐲𝐧𝐚𝐦𝐢𝐜𝐬 𝐚𝐧𝐝 𝐚𝐧𝐚𝐥𝐨𝐠 𝐟𝐫𝐨𝐧𝐭-𝐞𝐧𝐝. ⭐𝐓𝐎𝐅: 𝐓𝐡𝐞 𝐂𝐫𝐢𝐭𝐢𝐜𝐚𝐥𝐥𝐲 𝐃𝐚𝐦𝐩𝐞𝐝 𝐒𝐩𝐫𝐢𝐧𝐭𝐞𝐫 In TOF, a microchannel plate turns each ion hit into a nanosecond pulse sent over coax to a fast digitizer. Here everything is about clean transients: Underdamped → ringing, reflections, ghost peaks Overdamped → wide pulses, poor time resolution Designers therefore: Match the output to 50 Ω Minimize stray L and C Shape pulses for critical damping (fast, symmetric, no overshoot) On the ion-optics side, the reflectron provides second-order energy focusing: flight time becomes nearly insensitive to small energy spread → sharper peaks, higher resolution. 👉 TOF = critically damped electronics + second-order time focusing. It's where analog circuit theory meets analytical chemistry! Have 𝐅𝐔𝐍! #LCMSMS #AnalyticalChemistry #MassSpectrometry #Chromatography #Engineering

With deep respect and sincere humility, I want to share a perspective that challenges an idea held by HVAC professionals I admire greatly. Many of them have taught me, directly or indirectly, and I don’t take lightly the value of their experience or the weight of their insights. What I’m offering here is not meant as a contradiction, but as an invitation to dialogue and deeper understanding. When voltage is measured across the run capacitor of a PSC motor in operation, the RMS voltage will often read significantly higher than the supply voltage (e.g., 320 VAC on a 240 VAC system). It’s commonly believed in the HVAC community that this elevated voltage is caused by “back-EMF” from the motor. I respectfully disagree. I contend that this increased voltage has little, if anything, to do with back-EMF. Rather, I believe it is caused by a well-known AC phenomenon called voltage magnification. In a PSC motor, the start winding and run capacitor form a series LC circuit. At or near the motor’s operating frequency, the capacitive reactance of the capacitor and the inductive reactance of the winding can cancel each other out, resulting in series resonance. In the images, you will see where I made a little breadboard circuit with nothing but a few parallel 10μF capacitors and a 10mH inductor. I added capacitors to my capacitor bank until I approached resonance (about 70μF). I don't have the supplies to fine-tune it, but you can see how my supply RMS voltage is 5.56VAC and my RMS voltage across my capacitor is higher (5.82VAC). What do you think? Am I mistaken? Please comment! I am eager to learn! #hvac #electrialengineering #engineering #electricmotors

Some years ago I did an investigation on a fascinating ferroresonance (in short FR ) phenomenon, the mitigation has been incorporated in the IEEE PSRC WG 25 ‘Distance Element Response to Distorted Waveforms’. FR is a general term used to describe a variety of resonant interactions between capacitors and saturable iron-core inductors. This investigation was on a secondary FR due to energizing a line, and the presence of some undersized aux PTs used for sync. Upon switching or HS reclosing, a TOV up to twice the nominal voltage may be recorded on the secondary of a CCVT. If an Aux PT (a saturable inductor) is not sized appropriately it will saturate, thereby triggering FR. FR produces higher harmonics and sub-harmonics which distort the waveform. The problematic harmonics are typically a sub-multiple of the nominal freq.  For example, a nominal freq of 60Hz will display harmonics at 20Hz or 30Hz (Fig. 2). Sub-harmonic content will overexcite the Aux PT iron-core, driving it into saturation and thus overloading the voltage circuit. When saturation occurs it is common for fuses or MCBs to trip, leaving EM distance relays with no restraint quantity. With no restraint quantity and in absence of fault detectors these relays are subject to misoperate. The heating takes time and since the FR may be sustained the operator usually finds this when opening up the CCVT secondary box (Fig.1). The terminals are corroded due to the ionized air in the enclosure produced by the arcing of the protective gap. A typical CCVT is shown on Fig.3 and the mechanics of the FR for this investigation in Fig. 4 We then worked with an aux xfmr manufacturer and designed an xfmr which saturates only when the voltage is more than twice the Vn. Fig. 5 shows the excitation curves for various Aux PTs, no FR was triggered once the old Aux PTs have been replaced. Modern distance relays have embedded logic to block the operation in case of loss-of-potential (which can occur due to overloading the Aux PTs and CCVTs during FR). Fig. 6 is a record of a distance relay operation which overreached for an out-of-section fault. The FR condition was already present when the fault occurred. The system frequency (60Hz) and the relay sampling frequency (58.5Hz) do not match. The sampling frequency was different because of the sub-harmonic frequency (20Hz) superimposed to the fundamental frequency due to FR. The relay switched to the long memory time constant and "froze" the polarizing memory. The measured voltage and the polarizing voltage began to drift apart and consequently the relay tripped. It's therefore critical to size the Aux PT's properly. It is a mistake to assume that an Aux PT can "ride through" any transient produced by switching equipment (lines, transformers, etc.). The question is not if the Aux PT (or the CCVT FR suppression circuit) can handle the voltage surge. The relevant question is what type of Aux PT's should be correctly chosen to avoid FR from the beginning.

𝐔𝐧𝐝𝐞𝐫𝐬𝐭𝐚𝐧𝐝𝐢𝐧𝐠 𝐇𝐚𝐫𝐦𝐨𝐧𝐢𝐜 𝐀𝐧𝐚𝐥𝐲𝐬𝐢𝐬 𝐢𝐧 𝐏𝐨𝐰𝐞𝐫 𝐒𝐲𝐬𝐭𝐞𝐦𝐬: 𝐑𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞, 𝐓𝐲𝐩𝐞𝐬, 𝐎𝐜𝐜𝐮𝐫𝐫𝐞𝐧𝐜𝐞, 𝐚𝐧𝐝 𝐌𝐢𝐭𝐢𝐠𝐚𝐭𝐢𝐨𝐧 Harmonics are unwanted sinusoidal components of a waveform, often resulting from non-linear loads and electronic devices connected to the power grid. Among the various challenges posed by harmonics, resonance is a phenomenon that demands special attention. This post aims to provide insights into resonance in power systems, its types, the systems prone to resonance, and strategies for effective mitigation. 𝐖𝐡𝐚𝐭 𝐢𝐬 𝐑𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞? Resonance in power systems refers to the condition where the frequency of a harmonic component coincides with the natural frequency of a system, leading to a significant increase in the amplitude of that harmonic. 𝐓𝐲𝐩𝐞𝐬 𝐨𝐟 𝐑𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞: 🔶Series Resonance: Occurs when the inductive reactance equals the capacitive reactance in a circuit, leading to a sharp increase in voltage at the resonance frequency. 🔶Parallel Resonance: Involves the equality of the capacitive and inductive susceptance in a circuit, resulting in a drastic increase in current at the resonance frequency. 𝐒𝐲𝐬𝐭𝐞𝐦𝐬 𝐏𝐫𝐨𝐧𝐞 𝐭𝐨 𝐑𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞: 🔷 Capacitor banks: Capacitor banks, commonly used for power factor correction, can be prone to resonance if not properly designed. 🔷 Transformers: The interaction between the leakage inductance and the distributed capacitance of transformers can lead to resonance. 🔷 Transmission Lines: Long transmission lines with distributed parameters are susceptible to resonance, particularly due to the interaction of inductance and capacitance. 𝐇𝐨𝐰 𝐭𝐨 𝐌𝐢𝐭𝐢𝐠𝐚𝐭𝐞 𝐑𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞 𝐢𝐧 𝐏𝐨𝐰𝐞𝐫 𝐒𝐲𝐬𝐭𝐞𝐦𝐬: 🟣 Use of Tuned Filters: Tuned filters are designed to absorb specific harmonics and are effective in preventing resonance by adjusting their resonance frequency away from the critical system frequencies. 🟣 Damping Techniques: Adding damping resistors in series or parallel with capacitors can help dissipate excess energy and prevent the amplification of resonant frequencies. 🟣 Proper Design and Sizing: Ensuring proper design and sizing of equipment, such as transformers and capacitor banks, can minimize the likelihood of resonance. 🟣Active Harmonic Filters: These filters continuously monitor the system and dynamically adjust their parameters to mitigate resonance as it occurs. If you want to learn more comment below #powerprojects #powergeneration #transmission #powersystems #electricalengineering #harmonic #electricalengineering #renewables #renewableenergy