Inductor and Capacitor Performance at High Frequencies

You're switching at 2.2MHz with a standard input cap bank: 22µF, 1µF, 100nF, 10nF ceramic. The fundamental is clean. But the 2nd harmonic at 4.4MHz is failing conducted EMI by 10dB. You add more caps and it even gets worse. What's going on? Every ceramic cap has a self-resonant frequency where its impedance hits minimum. Below SRF it's capacitive. Above SRF it's inductive. When you parallel two caps, the frequency band where one is inductive and the next is capacitive creates an anti-resonance peak where the combined impedance actually increases. With decade-spaced values (22µF, 1µF, 100nF, 10nF), the SRFs fall at 1.3MHz, 7.1MHz, 25MHz, and 92MHz. None of them are on your harmonics. Worse, the anti-resonance between the 22µF and 1µF lands at 4.5MHz, right on your 2nd harmonic. Your filter is amplifying the one frequency you need it to suppress. The fix isn't adding more caps. It's choosing values so the SRFs land on the harmonics you need to filter. SRF = 1/(2π√(C×ESL)). For a given package with known ESL, you can work backwards from your target frequency to the capacitance value that resonates there. For a 2.2MHz converter, that gives you 6.8µF, 2.7µF, 1.2µF, and 820nF, each targeting the 1st through 4th harmonics. The result is the impedance at the 2nd harmonic drops from 53mΩ to 4mΩ. A 13× improvement from changing four component values. Same package sizes, same PCB footprint, same BOM cost. Stop picking decade values for your input caps. Design the SRFs to land on your harmonics. #PowerElectronics #EMC #CapacitorSelection

We obsess over shaving microamps in firmware while ignoring the real power vampire: power integrity collapse. After debugging three field failures in battery-powered medical devices, I’ve learned the hard way: Your firmware optimizations mean nothing if your power delivery network (PDN) is lying to you. Case Study 1: A "5µA sleep mode" IoT sensor kept dying overnight. Root cause? A 4.7µF ceramic capacitor’s resonant frequency (150MHz) coincided with the DC-DC converter’s switching frequency. Result: 200mA current spikes every 10ms, draining the battery in 6 hours instead of 6 months. Case Study 2: An automotive ECU resetting during cold starts. Issue? Voltage droop (-1.2V below nominal) when the fuel injector fired. The 3.3V rail dipped to 1.8V for 500ns, just enough to corrupt the RTC’s shadow registers. Why We Ignore PDN: Toolchain Blindness: Most embedded IDEs can’t simulate PDN impedance. We optimize code in a vacuum. Component Myopia: We select MCUs for "low power specs" but ignore that 80% of power issues stem from passive components. Frequency Illusion: We assume DC-DC converters "just work" without checking: Control loop stability (phase margin <45° = oscillations) Output capacitor ESR (too low = ringing; too high = ripple) Layout inductance (via stubs adding 2nH = 20mV overshoot) The Fix: PDN-First Design Step 1: Simulate PDN impedance (e.g., Keysight ADS) from DC to 1GHz. Target: <0.1Ω up to 50MHz. Step 2: Use mixed capacitor types: Bulk electrolytics (100µF+) for low-frequency stability X7R ceramics (1-10µF) for mid-frequency decoupling NP0/C0G (100nF) for high-frequency noise (>100MHz) Step 3: Layout rules: Place decoupling caps <3mm from MCU power pins Use 20mil+ power traces (reduce inductance by 40%) Split ground planes? NO. Use solid ground under switching components. The Ugly Truth: Most "low-power" designs fail because we treat power as an electrical problem, not a system-level physics problem. Your firmware’s sleep mode is irrelevant if your PDN is a noise generator. Question: What’s your worst power integrity horror story? Bonus points if it involved a capacitor resonance or ground bounce. #PowerIntegrity #EmbeddedDesign #PDN #EMI #Hardware

𝐃𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐃𝐞𝐦𝐲𝐬𝐭𝐢𝐟𝐢𝐞𝐝 𝐏𝐚𝐫𝐭 6: 𝐓𝐡𝐞 𝐮𝐥𝐭𝐢𝐦𝐚𝐭𝐞 𝐬𝐨𝐥𝐮𝐭𝐢𝐨𝐧…. ⚠️ Please check parts 1-5 of this series first. 💻 Say you need a power supply for a high performance CPU. For a single supply input the specs are as follows: ✔️The core voltage is 1V with 30mVpp 🚩 ripple allowed with current spikes of 20A 🚩 😱 So let this sink in: A 20A spike and just 30mV spikes allowed!!!! This means that any kind of resonance in your supply / decoupling network will crash your CPU. 💡This means that a decoupling network for a situation like this has 2 requirements: ➀ The impedance must be low. ➁ The Q factor of the network must be low (reduce parallel resonances) 💡 So how do you do that? By making your decoupling networks worse! 1️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐫𝐬𝐭 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a 𝐝𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐧𝐞𝐭𝐰𝐨𝐫𝐤 with a combination of 4 𝐡𝐢𝐠𝐡-𝐯𝐚𝐥𝐮𝐞 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫𝐬 degraded with 1 Ohm resistors? Why? To kill the Q factor. Modern capacitors have a ridiculously low 𝐄𝐒𝐑 (𝐑) by design, creating 𝐢𝐧𝐟𝐢𝐧𝐢𝐭𝐞 𝐐 (see formula). This is why ESR reducing resistors help. 2️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐬𝐞𝐜𝐨𝐧𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see another enemy in the fight against resonances: Unwanted inductance. 💡 Every trace has some inductance. 𝐈𝐧𝐝𝐮𝐜𝐭𝐚𝐧𝐜𝐞 𝐢𝐧𝐜𝐫𝐞𝐚𝐬𝐞𝐬 𝐐. So you want to use wide traces, or even better: Planes, they have the lowest inductance. 🚩 DC/DC converters and LDOs also have an 𝐢𝐧𝐝𝐮𝐜𝐭𝐢𝐯𝐞 𝐨𝐮𝐭𝐩𝐮𝐭. So there is always inductance! 3️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐭𝐡𝐢𝐫𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a simulation schematic to analyze the effects of degrading 𝐟𝐨𝐮𝐫 100𝐧𝐅 0805 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫𝐬 in parallel ( 🚩 this is just to show the effect, for a CPU supply, you’d need way more capacitance than this!!!). 4️⃣ 𝐓𝐡𝐞 𝐟𝐨𝐮𝐫𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞 you see the 𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧 and 𝐦𝐞𝐚𝐬𝐮𝐫𝐞𝐦𝐞𝐧𝐭 result of this network. You can see the test PCB as well. 📐 Results match quite well, you can see the impedance at high frequencies is lower in reality than in the simulations. This is due to the use of simplified capacitor models. 5️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐟𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a comparison with the traditional decoupling network you’ve seen in the first parts of this series. ✅ What clearly stands out is how ‘friendly’ the network with 1 Ohm resistors behaves. ⚠️ Now don’t go using this everywhere, most applications don’t need this more expensive overkill approach. It is good to have this in your toolkit however, should you ever encounter a situation like this. 🎬 I also have a video on this subject: https://lnkd.in/eVBtD_c9 🎓 And I have a course — you can watch a free module and get a free checklist here: https://lnkd.in/ews6cwQm Best regards and happy designing, Hans Rosenberg

What is parallel and series resonance with respect to harmonics. And how can capacitor bank filters mitigate this. Toolkit for visualizing this: https://lnkd.in/gEUhAvX4 This issue is coming up more and more with data centers and other large power electronic loads coming online. Most steady state harmonics in facilities are created by power electronics. VFDs, UPS systems, rectifiers, and anything that converts AC to DC and back again tends to inject harmonic currents. Saturation in motors and transformers can create distortion too, but it is usually more of a heating issue for that piece of equipment. The key point is that harmonic sources are usually modeled as harmonic current injections. That means the harmonic voltage distortion you see is largely set by the system impedance at each harmonic frequency and athe impedance is not the same at every frequency. Inductive reactance increases with frequency. Capacitive reactance decreases with frequency. So the system can be “stiff” at one harmonic and “soft” at another. If the impedance happens to peak at a certain harmonic, the voltage distortion at that harmonic can jump even if the harmonic current did not change much. That peak is usually the result of resonance. At the parallel resonant frequency, the effective impedance at the bus becomes high. High impedance at a harmonic means the injected harmonic current produces a larger harmonic voltage. This is why sometimes a capacitor bank install is followed by higher voltage THD. The harmonic current sources were already there. The capacitor changed the impedance profile. Series resonance is the opposite behavior. In a series resonant path, inductive and capacitive reactance cancel at a certain frequency, leaving a very low impedance path at that frequency. Low impedance means harmonic current at that frequency will preferentially flow into that branch. If that low impedance branch is your capacitor bank, the bank can absorb significant harmonic current and overheat. This is one reason capacitor banks cannot be treated as harmless bolt-on power factor correction in harmonic environments. A common approach is a detuned capacitor bank. You add a reactor in series with the capacitor bank and size it so the series resonant point is below the dominant harmonic, commonly below the 5th. The goal is to provide a low impedance path for that harmonic. Triplen harmonics act like zero sequence and want to go to a ground source but the concept of needed a low impedance path to avoid voltage distortion is the same. #utilities #electricalengineering #renewables #energystorage #datacenters #refineries

We’re often told to place decoupling capacitors as close to the IC as possible. But in high-speed design, that advice is an oversimplification. At high frequencies (f), what really matters is the impedance (Z) seen by noise 🔊. ⚡️ And this impedance isn’t determined by resistance 🚧. It’s dominated by the total inductance (Lloop) of the current path 🛣️ and the relationship is straightforward, Z ≈ jωLloop (where ω=2πf) This total loop inductance sets the capacitor’s self-resonant frequency (SRF), the point where it’s most effective. Once you go above its SRF, the capacitor starts behaving like an inductor, making it useless for suppressing high-frequency noise. To effectively tackle high-frequency noise, you need to minimize impedance by reducing the total loop inductance, which consists of, Lloop=Ltrace+Lcap_ESL+Lvia Focusing only on shortening the trace (L_trace) by a few millimeters often overlooks the bigger culprit: L_via ❌. The real objective is to shrink the entire loop area, which typically means prioritizing via placement 📌 to ensure the most direct connection 🛣️ to the ground plane 🟦. A well-placed via can be more critical than simply placing the capacitor physically close to the IC. ✅ The correct approach: First, determine the optimal via positions to create the shortest, most direct path from the capacitor pads to the power and ground planes. Then, place the capacitor in that optimal spot as close as practical to the IC power pins to keep the total loop inductance as low as possible. And don't Forget the Capacitor ESL. 🎯 Stop thinking in millimeters 📏. Start designing in nanohenries 🔬. #PowerIntegrity #SignalIntegrity #CircuitDesign #PCBDesign #HighSpeedDesign #EMC #EMI #ElectronicEngineering