FPGA Innovations

FPGAs have long been essential for high-performance computing, AI acceleration, and signal processing—but scalability and efficiency have remained persistent challenges. Enter Monolithic 3D (M3D) FPGA architecture, a breakthrough leveraging stackable back-end-of-line (BEOL) transistors to redefine FPGA design. 🔍 What Makes M3D FPGAs Game-Changing? Traditional FPGAs rely on Si-based SRAM for configuration memory, but M3D architecture integrates: ✅ N-type (W-doped In₂O₃) and p-type (SnO) amorphous oxide semiconductor (AOS) transistors in the BEOL ✅ More compact and power-efficient pass gates for reconfigurable circuits ✅ FPGA switch and connection block matrices stacked above configurable logic blocks (CLBs) 💡 The Results? 📉 3.4x reduction in area-time squared product (AT²) ⚡ 27% lower critical path latency for faster execution 🔋 26% lower power consumption in reconfigurable routing blocks 🔬 Why This Matters for Future Applications With leading foundries investing in BEOL-compatible AOS transistors, M3D FPGAs are poised to: 🧠 Accelerate hyperdimensional computing and large language models (LLMs) 🌍 Enable ultra-efficient edge AI inference and real-time signal processing 📡 Revolutionize next-gen telecom, radar, and high-frequency trading systems 🔑 The Road Ahead By interfacing with Verilog-to-Routing (VTR) tools, M3D FPGA designs in 7 nm technology are already demonstrating next-level performance gains. As device research and circuit design converge, we’re looking at a new era of FPGA efficiency, scalability, and power optimization. ⚙️ How do you see M3D FPGAs shaping the future of reconfigurable computing?

A few months ago, we shared with you our progress on developing novel decoding algorithms for qLDPC codes. That effort resulted in the Relay-BP algorithm (https://lnkd.in/eFbWNFeU), which surpassed prior state-of-the-art qLDPC decoders in terms of logical error rate while simultaneously removing barriers toward real-time implementation. In particular, we showed that a novel variation of the belief propagation (BP) algorithm was sufficient for accurate decoding of our gross code without the need of an expensive second-stage decoder to fix cases where BP failed to converge. I’m excited to tell you about some of the progress we’ve made on taking the first steps towards implementing a real-time decoder in hardware (https://lnkd.in/e8CShTmT). Our initial effort has focused on FPGAs because they are very flexible and allow for very low-latency integration into our quantum control system. FPGAs’ flexibility in supporting custom logic and user-defined numerical formats allowed us to evaluate the performance of Relay-BP across a range of floating-point, fixed-point, and integer precisions. Encouragingly, we observe a high tolerance to reduced precision. Our experiments show that even 6-bit arithmetic is sufficient to maintain decoding performance. We explored the speed limits of an FPGA Relay-BP implementation in a maximally-parallel computational architecture. Like traditional BP, the Relay-BP algorithm is a message-passing algorithm where messages are exchanged between nodes on a decoding graph. Our maximally parallel implementation assigns a unique compute resource to every node in this graph, allowing a full BP iteration to be computed on every clock cycle. This decoder architecture is resource-intensive, but we succeeded in building a Relay-BP decoder for the gross code and fit it within a single AMD VU19P FPGA. Our implementation is limited to split X/Z decoding of the gross code syndrome cycle (we decode windows of 12 cycles), a simpler implementation than we’d need for Starling. That being said, it is extremely fast, an absolute requirement for practical implementation. In fact, we can execute a Relay-BP iteration in 24ns. As physical error rates drop below 1e-3, Relay-BP typically converges in less than 20 iterations. This means we can complete the decoding task in about 480ns. This is significantly faster than what is possible with NVIDIA’s DGX-Quantum solution, which requires a 4000ns start-up cost before decoding begins. The figure below compares the logical error performance versus physical error rate of our FPGA implementation compared to a floating-point software implementation for memory experiments of the size of Loon and Kookaburra on our Innovation roadmap. This and further data shows that the reduced precision arithmetic in the FPGA matches the accuracy of a software model, while simultaneously running dramatically faster. Further details are in the pre-print: https://lnkd.in/e8CShTmT

Two years ago I started using AI to design FPGAs. Most people told me to fine-tune a private hardware model. The math said otherwise. 20 years hand-writing VHDL/Verilog for satellite image compression. A year and a half at UCLA's VAST Lab watching CS students treat FPGAs as a software problem. That was the first abstraction lift: RTL to HLS. The next one is here: HLS to AI. You write the architecture. AI writes the Verilog. Three lessons after running this at real scale. ▸ Use frontier public models. Claude Opus 4.6 hits 89.74% on VerilogEval with a lightweight reflection loop. Every base-model upgrade lifts your RTL quality for free. Private fine-tunes buy ~10% gain and need re-training on every version jump. ▸ Three pillars for productization: functional correctness, hardware efficiency, output stability. DSP cascades, BRAM vs SRL, zero bit-growth, truncation not rounding. Miss any one, the rest is wasted. ▸ Three LLM weaknesses will eat you alive: hallucination, forgetting, knowledge gaps. Fight them with structured generation, automated validation, and retrieval. General industry patterns, not domain tricks. Real results on Xilinx UltraScale+ RFSoC: N=1024 Radix-2² FFT at 445 MHz, 1021 LUT. For N=8192 the framework auto-picked a hybrid that hits 28 DSP instead of 52. A 46% saving a human under deadline might have skipped. If you're still hand-writing Verilog in 2026, you are solving the wrong problem at the wrong layer. #FPGA #AIforHardware #HardwareDesign #AIEngineering #Semiconductors

FPGA Engineering in 2026 vs 2016 ? Your mental model is outdated, if you learned FPGAs 10 years ago, FPGA engineering did not just evolve. It shifted from hardware-centric work to system-level problem solving. What changed? A lot. Back in 2016: • RTL was king • Tools were slower and less automated • Verification was often “good enough” • Most designs were local, self-contained • Software-FPGA boundary was clear Today in 2026: • Systems matter more than RTL • Toolchains are smarter—but more complex • Verification is a bottleneck (and a differentiator) • FPGA = part of a bigger compute system • HW/SW boundary is blurred The real shift Then: 👉 “Can you design this block?” Now: 👉 “Can you make the whole system reliable, scalable, and maintainable?” Where engineers struggle today? Not in writing RTL But in: • architecture decisions • integration with software stacks • performance vs power trade-offs • verification at scale • understanding full system behavior • timing closure in large system • CDC and reset strategy across domains Biggest mindset change In 2016: You were a digital designer In 2026: You must be: • system engineer • verification thinker • performance optimizer • sometimes even software-aware Meme line: Engineer (2016): “It compiles.” Engineer (2026): “It scales, integrates, and survives edge cases.” 😆 The real takeaway FPGAs did not get easier. They became more powerful - and less forgiving. If you want to stay relevant: • think beyond RTL • invest in verification • understand systems, not just blocks! Good luck! If you're building FPGA systems today and feel the complexity, you’re not wrong. The game has changed. Write a direct message!

AI is chasing GPU speed, but edge devices need smarter FPGAs. Are we missing the real opportunity? Hundreds of tests were run on 11 FPGA architectures across two process nodes. The results? A single design tweak reduced area by 40% and cut power consumption by 46%. But here's the paradox: GPUs dominate the AI race with brute force computing power. FPGAs, once the backbone of aerospace, healthcare, and telecom, seem sidelined. Why? AI 1.0 saw FPGAs as custom accelerators for neural networks. Flexible, yes, but inflexible applications meant limited growth. AI 2.0 brought token processing and foundation models. GPUs soared, while FPGAs focused on storage-intensive tasks. Now we’re at AI 3.0. The game has shifted to edge inference. Low-cost, high-efficiency computing. This is where FPGAs shine. DeepSeek proved that extreme performance isn’t always the answer. At the edge, balance is king: performance, area, power, and cost. FPGAs deliver that balance. Small architectural optimizations can unlock massive advantages. The AI era doesn’t need FPGAs to compete with GPUs-it needs them to complement GPUs. The question is: How do we design FPGAs for edge AI without sacrificing what makes them unique? Let’s trade scars so fewer devices die in the field. #AI #EdgeComputing #FPGA #DeepTech #Engineering