Common Issues in Custom High-Voltage System Design

Why Most SiC #Inverter Failures Are Layout Failures Forget blaming the #SiC die or the gate driver. At hundreds of volts and hundreds of amps, the thing that actually breaks is almost always copper and geometry, not silicon. At 800 V and multi-hundred-kW power levels, parasitics stop being “second order.” A few nanohenries of DC-link loop inductance will ring with device capacitances and kick V_DS into catastrophic overshoot at turn-off. We’ve repeatedly seen systems spike well beyond the rail simply because the caps and busbars weren’t essentially welded to the half-bridge. Key failure mechanisms I keep seeing in the lab and field: • DC-link loop inductance → huge overshoot. Any length in the high-current loop stores energy that gets dumped into the MOSFET at turn-off. Tighten that loop first. • Gate ↔ power loop coupling → false turn-on. Fast dv/dt pumps current through Miller capacitances. If the gate loop is loose, you get brief gate-source glitches that are enough to trigger shoot-through on SiC. • Uneven current sharing and resonances. Paralleled devices double di/dt but any trace-length mismatch produces a device that hogs the surge. Common-source inductance feeds back into timing and creates deterministic imbalance. • “Random” failures aren’t random. Simulators often under-represent parasitic loops. What looks safe on paper rings differently once copper, assembly tolerances, and temperature swing appear. Teams often react by tweaking gate resistances or adding snubbers. Those are band-aids. The real fix is architectural: design the switching cell and the power loop first, then pick devices. Practical design priorities that actually stop crashes: • Minimize DC-link loop L with laminated/balanced busbars • Place low-ESR bulk and HF caps millimetres from the half-bridge • Make gate loops ultra-compact and electrically isolated from power loops • Keep parallel device source inductance matched and symmetric SiC enables extreme switching, but it also exposes every #PCBLayout failing. If your inverter explodes on first power, don’t start by blaming the MOSFET. Rework the copper. Reliable SiC inverters start with power-loop architecture and layout, not the transistor. Image credit: EEWorld. The inverter shown is the #Hyundai IONIQ 5 800 V traction inverter, used here as a representative example of modern high-power SiC inverter layout. #PowerElectronics #InverterDesign #ReliabilityEngineering #ElectricVehicles #HighPowerDensity #MotorDrives

If you have ever written or reviewed a high voltage circuit breaker specification, you know the standards are dense. IEC 62271-100, ANSI/IEEE C37.04, C37.06, C37.09. But not all ratings carry equal weight. Most breaker specs look complete, but hey are not. A few critical ratings consistently cause the most confusion, the most procurement errors, and the most surprises during commissioning. Here are the ones I pay the closest attention to, explained. Rated short-circuit current. The interrupting rating is stated on a symmetrical RMS basis, but the application still has to be checked for asymmetrical duty and DC offset. In high X/R systems, the actual interrupting duty can exceed what a superficial nameplate check suggests. I have seen specifications where this was not verified until the fault study came back. Transient Recovery Voltage. TRV is one of the most overlooked and most consequential ratings. After the breaker clears the arc, the system imposes a recovery voltage across the contacts. If that voltage rises faster than the breaker's dielectric recovery, restrike occurs. The standard provides TRV envelopes for different fault types, but the actual system TRV depends on your network topology, transformer impedance, cable lengths, and grounding. Blindly copying standard TRV values into a spec, especially for non-standard duties or unusual network configurations, is a serious mistake. Close and latch current. This is the peak asymmetrical current the breaker must withstand when closing onto a fault. It is not the same as the interrupting rating. If the breaker is used in reclosing service, this becomes especially important, because it may have to close into a fault that has not cleared. Specifying the interrupting capability without verifying close and latch for your application can leave a real gap. Continuous current and ambient temperature. The continuous current rating assumes a defined ambient and installation condition. In hot climates, poorly ventilated enclosures, or high-density switchgear lineups, actual temperature rise can exceed what the rating assumes. This should be addressed in the specification, not discovered during installation. Dielectric strength and altitude. The breaker insulation level has to match the application, including power-frequency withstand, lightning impulse withstand, and where applicable, switching impulse withstand. Above 1000 meters, air density drops and dielectric withstand decreases. If your substation is at elevation, the specification must account for it. A well written breaker specification is not a copy of the standard. It is an engineering document that translates system conditions into equipment requirements. What is the most common gap you have seen in breaker specifications? And if you have experienced a TRV-related failure, I would be very interested to hear about it.

Converter Passes Conducted EMI but Fails Radiated EMI – Why This Happens? A question I often see during EMC testing: “Our converter passes conducted emissions, but fails radiated EMI. How is that possible?” Passing conducted EMI means your filtering, grounding, and line impedance control are doing their job on the power lines. Radiated EMI, however, is a different challenge altogether. Common reasons for radiated EMI failure: *High di/dt & dv/dt loops Fast switching edges create strong magnetic and electric fields, especially from poorly controlled current loops. *PCB layout issues Long gate loops, poor return paths, split ground planes, or large high-frequency current loops act as unintended antennas. *Cables behaving as antennas Motor cables, DC links, sensor wires, or even short harnesses can efficiently radiate noise above ~30 MHz. *Inadequate shielding strategy Passing conducted EMI doesn’t guarantee the enclosure, seams, vents, or cable entry points are RF-tight. *Common-mode noise dominance Radiated emissions are often driven by common-mode currents, not differential-mode noise that line filters typically address. Key takeaway: Conducted EMI ≠ Radiated EMI compliance Radiated EMI is primarily a layout, geometry, and field-coupling problem, not just a filtering problem. Typical fixes I see working in practice: ✔ Optimised PCB stack-up and HF current loops ✔ Gate drive edge-rate control ✔ Common-mode chokes and cable ferrites ✔ Shielded cables with 360° termination ✔ Better enclosure bonding and grounding EMC success is not about “adding more filters” — it’s about controlling where the energy flows. If you’re designing high-power converters, inverters, or fast-switching SMPS, always think EMI early in the design, not at the test lab.

The most expensive mistake in vehicle power systems is made before the battery is chosen. Not cell brand. Not BMS. Not inverter. Voltage architecture. I’ve seen this mistake repeated by experienced teams — founders, procurement leaders, system integrators. Everything looks “safe” at the approval stage. Then, months later: →Charging is slower than promised →Cables run hotter than expected →Inverters throttle under real load →ROI quietly erodes Nothing fails dramatically. The system just never delivers what was approved. The default assumption behind most projects? “12V is safer for vehicles.” It feels conservative. It feels familiar. And it almost never gets challenged in decision meetings. That’s the problem. Here’s the reality most teams learn too late: Voltage does not define safety. Architecture does. Same power. Very different physics. A 6 kW system means: 12V → ~500A 24V → ~250A 48V → ~125A And heat doesn’t scale linearly. It follows I²R. Double the current → 4× the heat. That’s where real risk hides: →thermal stress →connector aging →voltage drop →invisible efficiency loss Not in voltage labels. Why this single decision becomes expensive →Hidden operating cost Thicker copper, higher losses, faster degradation. →Structural bottlenecks Large batteries paired with slow charging paths. Capacity on paper. Friction in reality. →Delayed failure Problems appear months later — when redesign is politically and financially painful. The battery supplier gets blamed. The architecture never gets fixed. A decision guide leaders actually need This is not about being aggressive or conservative. It’s about matching architecture to energy scale: ≤10 kWh → 12V 10–16 kWh → 24V ≥16 kWh → 48V If energy keeps growing but voltage stays the same, you’re designing resistance into the system. The uncomfortable truth Low voltage isn’t safer. It’s just familiar. Mature systems aren’t built on habit. They’re built on architecture that scales with reality — energy size, charging paths, and future expansion. If you were approving the same project today: At what system size would you stop defaulting to 12V — and why? That single answer usually reveals whether a system will scale… or quietly struggle. #LiFePO4 #VehiclePower #EnergyStorage #SystemArchitecture #EngineeringReality #ProcurementLeadership #RVIndustry #VanConversion #MobilePower #OffGridEnergy

Back to Basics: PCB Clearance and Creepages Last week a client was working on some high-voltage PCBs and I thought it's a nice time to address those here as well. How do you design for High-voltage PCBs? Let's at least discuss a major aspect of design, for that you need to understand two key components, Creepage and Clearance. Clearance is the minimum spacing between 2 items in a PCB through air or Line of Sight. These could be track-to-track spacing, track-to-components, or component-to-components. Now creepage is the spacing between 2 items along the surface of the PCB. Check images for clarification. These differ in cases where there is a slot on the PCBs between 2 items, Clearance distance will be the straight line path between them, but creepage would be all the way around the slot. So it will be much higher. Now for high-voltage PCBs, these terms are important because high-voltage sections can always arc over from one section to another if the distance is too small. Hence you must give some sort of clearance or slots between. It depends on the environmental conditions(Humidity, dust), Altitude(Air pressure reduces with height so does the breakdown voltage of air) where your PCB is used, and the coatings you provide on the PCBs(Conformal or Soldermasks). The standards which govern these are mentioned in the guideline IPC 2221B document. Check the image for a table that tells you the minimum spacing needed between conductors for different use cases. For cases above 500V, multiply the voltage difference after 500V with the multiplication factor and add it to the row above. Use the table from IEC 60950-1 Device Safety standard for Creepage values. It contains a table for minimum creepage distances for different voltages and degrees of pollution the PCB might be subject to. Now next time you do high voltage designs keep the distances in mind. What are your favourite high-voltage design tips? #BackToBasics #highvoltage #pcbdesign #circuits

Common Issues Faced in H-Bridge of AC/DC (PSPWM and LLC) at operating Frequencies from 100 kHz to 250 kHz: 1. Dead short of high-side and low-side MOSFETs in no time:  a. Ensure that the low-side MOSFETs are in the ON state during the PWM OFF state to keep the boost strap cap at charged state.  b. Check for sufficient dead time. Higher gate resistance can cause overlap in high-side and low-side gate pulses, leading to shoot-through.  c. Ensure sufficient bootstrap capacitance to hold the gate voltage during the turn-on of the high-side MOSFET.  d. Verify that Vds ringing is within the MOSFET's limits. (Ideally, design to keep ringing at Vds to no more than 5% to get through EMI/EMC)  2. Leading leg S1 and S4 overheating in PSPWM.  3. Overheating of S4 alone.  4. Overheating of S1 and S4 under no-load conditions, but less loss under loaded conditions.  5. Overheating at the secondary-side MOSFET.  (problems from 2 to 5 requires clear understanding on switching sequence of both pri and sec Mosfets, optimized switching pulse, topology and proper magnetics design. Additional Notes:  Using an analog PWM controller may not offer much flexibility in adjusting the PWM. Implementing the PWM in a microcontroller requires careful attention to the sequence of how the PWM is turned ON and OFF, as this matters significantly.  (source of Image: https://lnkd.in/gg3cSQXC) #PowerElectronics #EVTechnology #EVCharger

High currents do lots of useful things ... and some very bad things. I recently had the chance to help with a #design #review. The team was young. Some were recently out of college. During the review, they went through all of the specifications and the schematics for their system. the team did a great job, everything was well documented and presented. They were wise enough to bring in experienced engineers to review the design. However, something bugged me as we went through the presentation. When they showed a circuit capable producing hundreds of amps something seemed off, but I couldn't place it at first. I've been doing lots of low power and signal work lately so everything matched my expectations ... at first. As the review continued, it finally settled in what needed attention. If there was a short circuit or even a #software error that put the system in the wrong mode, the current draw could exceed the capacity of the wiring harnesses and PCB traces. The results could range from something relatively infuriating like burning a wire out to something dangerous like starting a fire. Odds were it would not be a problems on a first-of-a-kind prototype. The device would always have someone nearby. The consequences would likely be discovered and addressed quickly. However, expensive tests might be ruined, irreplaceable time lost, and reputations lost. A simple dollar part is all that is needed to prevent these problems. That additional dollar could save thousands of time that amount in debug time, repairs, and lost opportunities. Fuses in high power applications are a must. Several things could have improved the design and review process. 1) Adding a high level #FMEA and #FunctionalSafety review as part of the design review. 2) Leveraging existing ISO, IEEE, SAE International, UL, regulatory, and other standards to see how similar industries handle design problems like this. 3) Look at certification in similar industries. 4) Look at reference designs and guidelines for key high power components. Fortunately, the team filled the gaps in their experience with experts. They learned quickly and cheaply. This will should not be a problem for them moving forward. It great to move fast and break things. Its even better to avoid breaking things that could be avoided with a 5 minute discussion! ... Of course even if they do everything right, Murphy's Law can still rear its head! "If a fuse can blow, it will blow, and it will likely do so at the most inconvenient time." #deeptech #hardtech