Capacitor Design Strategies for High Power Systems

We’re often told to place decoupling capacitors as close to the IC as possible. But in high-speed design, that advice is an oversimplification. At high frequencies (f), what really matters is the impedance (Z) seen by noise 🔊. ⚡️ And this impedance isn’t determined by resistance 🚧. It’s dominated by the total inductance (Lloop) of the current path 🛣️ and the relationship is straightforward, Z ≈ jωLloop (where ω=2πf) This total loop inductance sets the capacitor’s self-resonant frequency (SRF), the point where it’s most effective. Once you go above its SRF, the capacitor starts behaving like an inductor, making it useless for suppressing high-frequency noise. To effectively tackle high-frequency noise, you need to minimize impedance by reducing the total loop inductance, which consists of, Lloop=Ltrace+Lcap_ESL+Lvia Focusing only on shortening the trace (L_trace) by a few millimeters often overlooks the bigger culprit: L_via ❌. The real objective is to shrink the entire loop area, which typically means prioritizing via placement 📌 to ensure the most direct connection 🛣️ to the ground plane 🟦. A well-placed via can be more critical than simply placing the capacitor physically close to the IC. ✅ The correct approach: First, determine the optimal via positions to create the shortest, most direct path from the capacitor pads to the power and ground planes. Then, place the capacitor in that optimal spot as close as practical to the IC power pins to keep the total loop inductance as low as possible. And don't Forget the Capacitor ESL. 🎯 Stop thinking in millimeters 📏. Start designing in nanohenries 🔬. #PowerIntegrity #SignalIntegrity #CircuitDesign #PCBDesign #HighSpeedDesign #EMC #EMI #ElectronicEngineering

You check the Voltage rating. You check the Capacitance. You might even check the temperature rating. But if you ignore ESR (Equivalent Series Resistance), you are building a time bomb. In my 38 years of diagnosing faults—from semiconductor RF generators to nuclear power systems—I’ve seen more failures caused by "correct" capacitors than "wrong" ones. Here is the physics rookie engineers forget: Ripple Current creates heat. The formula is simple: P = I_{ripple}^2 *ESR. If you have a high-switching-frequency power supply (like the ones I worked on at Superpower Inc. and Globalfoundries), that ripple current is significant. If you replace a Low-ESR capacitor with a generic "general purpose" one from the bin, that internal resistance turns your capacitor into a heater. The electrolyte boils. The pressure builds. The vent pops. And suddenly, your critical asset is offline. When I was rehabilitating those 54 nuclear-grade power supplies, we didn't just match the microfarads. We looked at the dissipation factor and ESR at the specific switching frequency. Because in a sealed enclosure, heat has nowhere to go. The Takeaway: If you are designing a HAT for a Raspberry Pi or repairing a vintage amplifier, stop buying the cheapest bag of caps on Amazon. Look at the datasheet. Low ESR isn't a luxury; in modern switching circuits, it's a requirement. #PowerElectronics #ESR #Capacitors #ReliabilityEngineering #Obsolescence #SpencerSmith #FailureAnalysis

Most engineers size their input capacitors based on voltage ripple but might forget to check what the capacitor technology costs them in thermal losses. This choice matters more than you might think. The buck converter input current is pulsed. When the high-side switch is on, the full Iout flows from the input source through the switch. When it turns off, the input current drops to zero. The entire AC component has to be handled by the input capacitor, and the RMS works out to: I_Cin_rms = Iout × √(D × (1-D)) That parabola peaks at D = 0.5 where I_Cin_rms = Iout / 2. For a 10A converter, that's 5A RMS flowing through your input bank. Nothing unusual about that number. The interesting question is what 5A RMS actually costs you depending on what capacitor technology you pick as ESR varies by almost two orders of magnitude across common technologies. A typical 10µF X7R ceramic at 500kHz has around 2.5mΩ of ESR which at 5A RMS is 62mW dissipation. Switch to a 10µF polymer at 15mΩ and you're at 375mW dissipation. Switch again to a 10µF aluminium electrolytic at 100mΩ and you're dissipating 2.5W in a single capacitor. 2.5W in a cap the size of your little finger runs hot. Electrolytic lifetime halves for every 10°C rise above rated temperature, so that thermal stress directly translates into reduced service life. Using electrolytics isn't always wrong, they're cheap, they hold their capacitance with voltage, and they're fine for low duty cycle applications where RMS stress is modest. But if your converter lives anywhere near D = 0.5, which covers 48V to 24V, 12V to 6V, 5V to 2.5V, and plenty of others, the ESR of your input cap choice is a first-order design decision. Check your input cap technology against the RMS your converter will actually impose, not just the voltage rating and capacitance. Paralleling smaller capacitors is also a useful way of bringing down the ESR and dissipation. #PowerElectronics #BuckConverter #CapacitorSelection

We obsess over shaving microamps in firmware while ignoring the real power vampire: power integrity collapse. After debugging three field failures in battery-powered medical devices, I’ve learned the hard way: Your firmware optimizations mean nothing if your power delivery network (PDN) is lying to you. Case Study 1: A "5µA sleep mode" IoT sensor kept dying overnight. Root cause? A 4.7µF ceramic capacitor’s resonant frequency (150MHz) coincided with the DC-DC converter’s switching frequency. Result: 200mA current spikes every 10ms, draining the battery in 6 hours instead of 6 months. Case Study 2: An automotive ECU resetting during cold starts. Issue? Voltage droop (-1.2V below nominal) when the fuel injector fired. The 3.3V rail dipped to 1.8V for 500ns, just enough to corrupt the RTC’s shadow registers. Why We Ignore PDN: Toolchain Blindness: Most embedded IDEs can’t simulate PDN impedance. We optimize code in a vacuum. Component Myopia: We select MCUs for "low power specs" but ignore that 80% of power issues stem from passive components. Frequency Illusion: We assume DC-DC converters "just work" without checking: Control loop stability (phase margin <45° = oscillations) Output capacitor ESR (too low = ringing; too high = ripple) Layout inductance (via stubs adding 2nH = 20mV overshoot) The Fix: PDN-First Design Step 1: Simulate PDN impedance (e.g., Keysight ADS) from DC to 1GHz. Target: <0.1Ω up to 50MHz. Step 2: Use mixed capacitor types: Bulk electrolytics (100µF+) for low-frequency stability X7R ceramics (1-10µF) for mid-frequency decoupling NP0/C0G (100nF) for high-frequency noise (>100MHz) Step 3: Layout rules: Place decoupling caps <3mm from MCU power pins Use 20mil+ power traces (reduce inductance by 40%) Split ground planes? NO. Use solid ground under switching components. The Ugly Truth: Most "low-power" designs fail because we treat power as an electrical problem, not a system-level physics problem. Your firmware’s sleep mode is irrelevant if your PDN is a noise generator. Question: What’s your worst power integrity horror story? Bonus points if it involved a capacitor resonance or ground bounce. #PowerIntegrity #EmbeddedDesign #PDN #EMI #Hardware

𝐃𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐃𝐞𝐦𝐲𝐬𝐭𝐢𝐟𝐢𝐞𝐝 𝐏𝐚𝐫𝐭 5: 𝐀 𝐦𝐮𝐜𝐡 𝐛𝐞𝐭𝐭𝐞𝐫 𝐝𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐬𝐭𝐫𝐚𝐭𝐞𝐠𝐲! In parts one to four of this series, we went through the capacitor model, simulation methods, Q factor, and a very common decoupling network that turns out to work very badly. In this part, we’re going to look at superior solutions. 1️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐫𝐬𝐭 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a 𝐝𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐧𝐞𝐭𝐰𝐨𝐫𝐤 with a combination of 4 𝐡𝐢𝐠𝐡-𝐯𝐚𝐥𝐮𝐞 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫𝐬 and a test board used to measure it. Why 4 high value capacitors? 💡 The high capacitance kills the Q factor. 💡 Because they all have the same value, they all transition from capacitive to inductive (see 𝐩𝐚𝐫𝐭 1 in the series), which means they don’t create extra parallel resonances! You’ll just get a 𝐬𝐢𝐧𝐠𝐥𝐞 𝐝𝐞𝐞𝐩 𝐬𝐞𝐫𝐢𝐞𝐬 𝐫𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞. These don’t “hurt” since they don’t cause supply ringing when exposed to a load current pulse. 💡 This solution is also 𝐜𝐡𝐞𝐚𝐩𝐞𝐫 since you only need 𝐨𝐧𝐞 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫 𝐯𝐚𝐥𝐮𝐞 instead of three or four, and your production becomes easier with a 𝐬𝐦𝐚𝐥𝐥𝐞𝐫 𝐁𝐎𝐌 (Bill of Materials). You may wonder: why four? Can I not use a single 100nF capacitor? And you would be right, this will solve the parallel resonance problem as well! Putting four in parallel does have the advantage of creating a lower RF impedance since you now have four parallel paths to decouple. Four larger capacitors in parallel also increase the local energy storage, making the network more resilient for load pulses. 2️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐬𝐞𝐜𝐨𝐧𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a simulation schematic of this network in a 50-Ohm measurement system (see earlier parts in this series for more details). 3️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐭𝐡𝐢𝐫𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see the simulation result and a measurement result. They are quite close! The RF suppression is slightly better for the real circuit due to the use of first-order RLC models, which have some limitations. 4️⃣ 𝐓𝐡𝐞 𝐟𝐨𝐮𝐫𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞 shows my measurement setup: A NanoVNA connected to a laptop running NanoVNAsaver. 5️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐟𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a simulation of how these networks behave when hit with a load current pulse. The classic decoupling approach shows ringing. The 4×100nF approach does not ring at all and the voltage drops less, due to the higher total capacitance, making it much 𝐦𝐨𝐫𝐞 𝐫𝐨𝐛𝐮𝐬𝐭 𝐟𝐨𝐫 𝐥𝐨𝐚𝐝 𝐩𝐮𝐥𝐬𝐞𝐬. It can store more energy. 👉 In the next part, I’m going to show you the ultimate decoupling strategy. 🎬 If you can’t wait for that, check this video: https://lnkd.in/eVBtD_c9 🎓 𝐈 𝐚𝐥𝐬𝐨 𝐡𝐚𝐯𝐞 𝐚 𝐜𝐨𝐮𝐫𝐬𝐞 — you can watch a free module and get a free checklist here: https://lnkd.in/ews6cwQm Best regards and happy designing, Hans Rosenberg