Usefulness and Goals Achieved By An Introduction Of UVM Methodology
In recent years, UVM methodology has taken over the verification domain. UVM which is known as Universal Verification Methodology has been one of the pillars of verification. The main goal behind introducing the UVM methodology was to have common methodology for developing the verification environment across the globe. The main advantage behind having unique methodology is that every verification engineer can understand the enviournment easily. The main advantage of UVM is its one of the ways in which it can be used. UVM has one of unique way of creating components which can be re-used in future. This advantage comes with unique way of creating an environment. Once, environment is created then it is easy to be understood by any verification engineer who knows UVM around the globe. Apart from it, biggest goal which was achieved by introduction of UVM methodology was to reuse the same environment for multiple projects. UVM provided the way to reuse the different verification components for various projects. Another advantage of UVM is having the unique way of verifying the SOC environments with reusing the sequences for multiple IP's having the virtual sequences and virtual sequencer concept. There is a method of overriding any components in UVM environment which can be reused for verification. UVM scripts are provided which can create the complete environment withing few seconds. Only, internal code needs to be updated. Adding the code in an environment where updates needs to be done in terms of internal logic of blocks which are provided. All these advantages has made UVM one of the best methodology to be used for verification. All the countries around the globe is using the UVM for verification.
Why do we code manually? It should be fully automatic via Spec.
Before learning UVM verification engineers should learn OOP concepts. As already mentioned UVM increases degree of reuse but the verification work need to be still thought thoroughly. In addition we should not forget that formal verification is spreading much faster then UVM and for verification task is much better as not based on simulation. I believe that future of verification belongs more to formal rather then Simulation. Clearly simulation will never go away. Its use will be mainly for seeing high logic depth behavior.
Verification methodologies do enhance productivity but they are getting more attention than they really deserve. Let's not confuse the initial speed in bringing up the framework for real work of verification. Many times this framework may not even be natural fit for the problem. Just because its available quickly and used everywhere there is danger of force fitting every problem in to it. What do you think?