Importance of Verification IPs(VIPs) in Modern Verification!

There is a new era started in verification in terms of having the Verification IP(VIP) used for both IP and SoC verification. Verification IPs(VIPs) has simplified the way in which verification carried out of any complex SoC's having multi-million gates. Verification IPs (VIPs) can be developed in System Verilog, System having UVM/VMM/OVM methodologies. These VIPs are worth millions of dollars in terms of license coasting to end users. These are developed by premier tools companies like Cadence, Synopsys and Mentor Graphics. There are VIPs to verify PCIe, USB, SATA, SAS, Fiber Channel and Ethernet Protocols are available in the market.

These Verification IPs (VIPs) developed with targeted verification features which make them unique compared to other verification techniques. Verification IPs(VIPs) has most important feature in terms of having the in-built error injection and flexibility in configuration which help finding the complex bugs in design easily. Error injection can done through callbacks, factory methods or special bus monitor features which allow them to corrupt any outgoing transactions. These callbacks capture transactions going on to the bus and corrupts it before reaching the design. There are other mechanisms like active bus monitors(introducing random noise) which can corrupt the transactions going on an interface as well.

Verification IPs (VIP) are developed with various configuration to verify various aspects of design. Same Verification IP can work in various modes as per required by different designs. These kinds of configuration mechanism allow same Verification IP to work to act in different mode. Example, PCIe Verification IP(VIP) can be configured to work as switch, endpoint, or root complex with built-in configuration classes. It makes integration and verification of various design really simple and less time confusing. It makes testbench development simpler compared to any other modes of verification.

Another important feature of (Verification IPs) VIPs is inbuilt developed protocol violation checkers. There is VIP monitor integrated on interface between Design and Verification IP. It can be used to monitor transactions on bus and can be used to verify protocol rules automatically. Also, protocol rules can be developed as part of verification IP at various logical partitions. Whenever any transactions are sent or received from DUT then in-built protocol checkers developed in Verification IP can trigger error on protocol violations. Verification IP can throw errors which are mapped to specification and can help verification engineers to file bugs against design specification easily without knowing the protocol specification without any details. This method can provide protocol checking on each transaction. Example, PCIe protocol violations can be implemented as part of protocol checker from specification as part of Verification IP. It can check for protocol rules mapped to specification on an every TLP and DLLP received from design. It can pinpoint design bugs to designers. Designers can fix those kinds of bugs mapped to specification in short duration without looking at specification as well. 

Apart from it, Errors can be reported with various verbosity to verification engineers and debuggers using Verification IP feature. We can mask or demote any errors or protocol violations in case of those are known design issues. Also, we can configure Verification IP(VIP) to bypass or enable/disable any flow if its not supported by design. Example, we can bypass LTSSM in PCIe Verification IP if it’s not implemented in PCIe design at an initial stage of design. It can be very important feature which can help designers to verify design at an earlier stage in stead of waiting for other modules of designs gets completed.

Also, VIPs has in-built protocol specific functional coverage and assertions implemented which can be used for coverage closure of that design verification.

Overall, In Modern era Verification IP(VIPs) provides many features which can be useful to verify the design. It comes with features like error injectors, protocol checkers/assertions, various configurations, in-built functional coverage and ease of testbench development.

Now a days, Every MNC uses Verification IP to verify their design and find bugs faster with ease.