Toward General-Purpose Dynamic Dataflow Architecture, development log vol.1

I'm excited to share the first entry in my development log. During my PhD at NUS, I discovered an inspiring research topic—and now my life’s goal: realizing a general-purpose dynamic dataflow architecture, which also became my thesis topic. My team, RiDM (short for “RiDM is a Dataflow Machine”), secured initial investment from NUS to commercialize this concept. However, securing further resources to continue and scale our journey has been challenging. I’m writing these development logs with the hope of attracting investors, clients, or collaborators who want to join us in bringing this vision to life.

Yesterday, I confirmed that my RTL design was working well using ChiselTester. Although I knew it should work, finding the right branch and recalling commands took some time. Today, I ported the design to an AMD-specific RTL kernel and added interface modules to utilize the board’s memory for feeding Fibonacci function instructions to my dataflow machine. I also sketched the design overview (apologies for the hand-drawn diagram instead of a Visio version).

Adding the AXI interface modules was fairly straightforward, thanks to AMD’s tutorial. However, it’s been frustrating that hardware emulation doesn’t generate detailed waveforms within the RTL kernel, and the compilation process takes a long time even for emulation. This slows progress and limits the number of trial-and-error iterations I can perform. Fortunately, I achieved the same results as with ChiselTester, with hardware emulation allowing me to log data using fwrite in Verilog.

I am waiting for the hardware binary compilation, but I guess I need some sleep before getting the result, which I hope to be okay. Tomorrow, I plan to add a memory access channel to enable data transfer. If time permits, I’ll also try adding a separate clock to the RTL kernel to reach a higher operating frequency.