Exploring PID Control with a Dataflow Machine

Exploring PID Control with a Dataflow Machine

Last week, I had an interesting opportunity to present our technology to a potential client and discuss its applications. During the meeting, I was asked whether our dataflow machine could function as a PID controller. Despite having no prior knowledge of PID controllers—stemming from my background in pure mathematics during my undergraduate studies—I confidently responded that our architecture could handle it.

After the meeting, I delved into research by reading a paper and the Wikipedia entry on PID controllers. Then, I decided to implement one using our dataflow architecture.

Simplifying the Design


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Simplified hardware design. The scratchpad is removed as it is not required, while AXI_T channels are added to handle streaming data in and out.

To adapt our dataflow machine for this task, I made several optimizations:

  • Removed the scratchpad memory. Since the dataflow machine processes data streams efficiently, this component was unnecessary.
  • Added AXI_T channels for seamless data streaming in and out of the system.

The simplified hardware architecture now directly supports PID computations as data streams flow through.

The Dataflow Graph


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Dataflow graph of the single variable PID controller

I designed the PID controller as a dataflow graph with nine nodes, performing the fundamental operations of a PID controller:

  1. Calculating proportional, integral, and derivative terms based on error values over time.
  2. Multiplying coefficients with errors to compute control signals.

This implementation showcases the flexibility and efficiency of our architecture in handling diverse tasks.

Results


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The graph above demonstrates how the control variable converges to zero over 100 iterations. Despite selecting coefficients almost at random, the controller converged rapidly. This highlights the robustness of the PID concept, which models control signals by incorporating historical trends and current states.

  • Hardware Updates: Streamlined architecture with AXI_T channels replacing the scratchpad memory.
  • Dataflow Graph: Compact and efficient representation for PID computation.
  • Error Convergence Graph: Rapid convergence validates the implementation's effectiveness.

Closing Thoughts

This exercise reaffirmed my belief in the adaptability of our dataflow architecture. The ability to implement such a control system with minimal design changes opens the door to a wide range of industrial applications. If you're interested in exploring how our dataflow machine can solve your computational challenges, feel free to reach out!

Enjoy short but insightful article a lot , please continue the good works

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