Three Selected VHDL-2017 Features in Action

Patrick Lehmann is giving a talk on 13th July at FPGA Kongress in Munich, Germany. He'll talk about three new features in detail and present real world examples.

Three Selected VHDL-2017 Features in Action

VHDL-2017 brings a lot of new features from syntax regularization to incredible new APIs and packages. This talk will dive into three new features by example and unveil how they work.

1. Incomplete Types and Anonymous Types

VHDL enables us to write generic design units like a 4 input multiplexer that handles any std_logic_vector of any input size. But we still need to know the type of the multiplexer’s ports, right? What if we could spare even this knowledge and create a multiplexer for any type? 

Part one will dive into the new extensions for generic types and how type classes and incomplete types make them finally usable for the daily work. Based on generic types, a clever transformation is then presented that unveils the magic of anonymous ports to truly build a universal multiplexer.

2. Reflection API

Is it possible to create a to_string function that formats any deeply nested record-array data structure into a string representation? With VHDL-2017 we added this capability.

Part two will present a step-by-step guide on how to implement a universal to_string function. It will make use of pointers to protected types and dynamic allocation of protected types. Finally, an excerpt of the new Reflection API is used to implement the desired feature.

3. Mode Views and 'Spaceships'

Are you tired of wiring an seamlessly infinite number of signals from one instance to another instance? Have you always wished that a single record could handle all the signal routing from A to B?

In part three, a solution called mode view is presented that easily connects instances with just a single wire. The new concurrent signal association operation ('<=>', aka spaceship) is demonstrated that doesn't create new delta cycles in a simulation model.