[Algorithm] PLL Part I – Design of a Phase Locked Loop Providing Detailed Procedure to Compute Bandwidth, Kp and Ki values
• Power converters inherently need a Phase Locked Loop (PLL) to remain in-sync with the grid voltage
• PLLs provide the grid frequency and phase information which later can be used for control purposes
• The output of PLL is usually sine and cosine signals of unit amplitude, called unit vectors
• In this implementation of Synchronous Reference Frame PLL (SRF-PLL), which is a widely used PLL for grid-connected systems is presented
The underlying principle of SRF-PLL is that, once the input quantities have been converted to the reference frame, the desired reference vector is aligned with one of them, in this case, it is aligned to the q axis. Therefore, the projection of the desired vector on q axis is 100%.
In SRF-PLL, d component is chosen as the reactive component and q is chosen as the active component. In this implementation, d component is forced to zero to ensure unity power factor.
Additional details related to the small-signal state-space model of SRF-PLL can be found in the following publication, A. Kulkarni and V. John, “Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage,” IET Power Electronics, vol. 8, no. 12, pp. 2435-2443, 2015.
In this article, the focus is to organize the design steps in a sequential manner while elucidating all the intermediate mathematical computations to arrive at the values of bandwidth, Kp and Ki values needed for practical implementation.
The images and the experimental waveform are screenshots of a section in my Ph.D. thesis.
Input Phase A voltage is in-sync with the current drawn from the same phase (Channel 1 scale: 100 V/div, Channel 4 scale: 2 A/div, timescale: 10 ms/div).
The converter used is the Three Phase Three Switch Rectifier.
#random...why dont you use IQmathlib from TI?