Is Something Wrong?
In the summer of 2010, I found myself newly appointed as VP/GM of a $50M business unit at AppliedMicro (AMCC): Connectivity Products. An acquisition was in play for a company in Denmark that had the potential to fill a hole in our product roadmap. Its business model, however, was fundamentally different than anything we had done before: it uses FPGAs as the silicon vehicle for standard semiconductor products. After some final diligence and a gut check with CEO and Board of Directors, we forged ahead and completed the acquisition. The journey was fascinating. Below is the prologue of a manuscript I've written about the experience. Good reading!
George Jones
PS By 2014, Connectivity Products annual revenue exceeded $100M.
The semiconductor industry has evolved over the last forty years through predictable, regular, and dramatic cost reductions. The industry’s growth drivers: insane cost reductions, orders of magnitude performance increases, and virtually limitless production capacity. It is now a >$300B industry, powering everything from smartphones, to the Internet, through to deep space probes. Documented evidence of Moore's Law is legendary and real: double the density every 18 months, along with cost and performance benefits. Moore has been right for a long time. Looking forward, many believe that his law will no longer apply. The industry is in a troubled state, where innovations are not occurring at nearly their historical rate. Unprecedented consolidation into fewer mega-companies only makes the problem worse. Systems companies often do not have a clear path to break-through new architectures, because radically new chips are not being developed.
The central problem: semiconductor economics have stopped working for those who can innovate.
The move from two- to three-dimensional lithography, combined with fundamental changes in the physics at feature sizes below 20 nanometers (nm), breaks Moore's Law. Combined with exponentially more complex (and expensive) design tools and a step-function increase in the capital cost of a mask set, the financial hurdle to justify a new chip design project has become so high that only the highest volume and margin markets can justify a new chip. This is an interesting argument, because doesn’t it, in effect, say that Moore’s law now only functions for very high volume products?
Adaptation
What's astounding is that semiconductor standard product companies, those that define themselves as ASSP producers, continue acting as if their world has not fundamentally changed. Are they fooling themselves into believing that a new generation can exceed the "hurdle" of lifetime profit exceeding the cost of development by an acceptable multiple (typically at least 3x)? Are they left to face the facts: a choice between staying with older 2-dimensional process nodes, with no underlying improvement, or severely cutting back the number of new products developed using 14nm three dimensional processes? Naysayers suggest that a 28-nm process node has legs. But even 20-22-nm node technology is unlikely to advance designs to the power/performance levels that new smart phones, servers, network routers, and switches will require.
In reality, only the largest semiconductor companies can afford to develop new products. Their supply chain costs from wafer fabricators forward are so much lower than those of smaller companies that the hurdle rate can be exceeded on many more new chip developments. Now comes the real downer: the design innovations that have historically come from smaller upstart semiconductor companies have all but disappeared. Bigger suppliers are not incentivized to develop fundamentally new architectures or introduce new, unproven product categories. Quite simply, it represents too much risk, and the cost hurdle will not be satisfied to justify a fundamentally new product family. The icing on the cake: startup semiconductor companies - the historical source of new and innovative architectures - have rarely been funded in the last five years and are very low on the list of favored domains for most angel investors and venture capitalists. All of this begs the question: where will innovation come from if big semiconductor companies will not do it and startups cannot get funded?
These conditions add up to a serious and fundamental flaw in today's electronics industry. Device and systems companies are faced with some depressing options:
- Vertically integrate and architect chips from scratch
- Live with minor incremental upgrades from their semiconductor supply base
- Increase hardware development budgets to include the IP required to design in FPGAs, or
- Differentiate only in software
There are examples of where each of these approaches is satisfactory. But for many systems companies, none of these choices really works.
A Very Different Option
There is another alternative: Software Defined Chips - designs that run on FPGAs programmed and marketed as standard components. They are analogous to ASSPs (Application Specific Standard Products), which are purpose-built chips that systems companies have designed for many years. FPGA companies, such as Xilinx and Altera, have the capital and design wherewithal to build chips that can be programmed to perform most any imaginable function. The economics work because a single chip design can be used for a number of applications. But there is a flaw: the mindset of FPGA companies. They see their markets as systems companies who do FPGA designs along with their boards and systems. They do not recognize that innovative component companies can use their products and expand their total market. The budget and design talent at systems companies for designing complex FPGAs is waning. Systems hardware development groups are shrinking, not growing. Ask any systems company VP/GM you know about her budget for hardware development this year as compared to three years ago. If the number is as much as 75%, prepare to be surprised!
There are plenty of semiconductor hardware development teams and third party developers of IP; however, their hands are tied by the economics of three-dimensional, sub-20 nanometer processes. Despite these shackles, they almost never consider a Software Defined Chips approach.
So, how do Software Defined Chips do the job? They are designed by independent teams who know the applications cold. Their systems content has been fully thought-through: they work like an ASSP - very familiar territory for systems developers. They come with a complete standard data sheet, Applications Programming Interface (API), and a user-friendly development system. A systems development team can make progress with Software Defined Chips from the very first day using supplied evaluation hardware and a suite of configuration tools, easy to use APIs, and sample applications. Such a systems development team can deliver innovative board and systems designs while radically reducing time to revenue – and at a total cost that works. Seem crazy? Yes. Feasible? You bet. Been done? Absolutely.
This writing is dedicated to the proposition that the semiconductor industry can enter a new growth phase and provide its customers with innovative designs overcoming the hard cold reality of today's economic hurdles. All it takes is a mindset change.
Want to learn more? Check my consulting site, http://synthconsulting.com.
Copyright @ Synthesis Consulting LLC. All rights reserved.
In decades past, algorithmic value was often captured in the design of the silicon. For years I saw many innovations come into the market in the form of new chips from a variety of highly innovative small to medium-sized semiconductor companies. This was true in graphics, audio, video, communications (tele-, data-, wireless, etc.), mass storage, and a variety of technical fields. But today this is no longer the case. ASSP vendors who continue on in the belief that they can win by creating a chip which encompasses more innovative algorithms are fundamentally missing the reality of today's semiconductor industry. Today the value of the algorithms has migrated to software. That may mean code running on a processor core, or programming that configures programmable structures. In either case, the algorithms are developed in "soft" technology, so that they can be updated and revised at speeds and costs that are orders of magnitude better than if implemented in silicon. What good is your "highly efficient" chip design if my algorithms have had multiple additional generations of innovation and improvement in the time it has taken you to implement your silicon? If you seek to provide value through algorithmic innovations, you can not afford to work in silicon. You need to find a suitable IC platform, and focus on writing code for it. Your algorithms will evolve and improve faster.
Thomas, I don't see where SDCs replace fabless. There are many applications that have the volume and require optimization and functionality that can only be accomplished using tightly designed, purpose-built chips. And, there are a lot of systems that can function perfectly well with a general purpose processor. It's the (increasingly frequent) confluence of design & fab tooling/manufacturing overhead exceeding a production profit stream that SDCs can service well. That's the hurdle problem that general managers face and have real trouble solving.
Very insightful writing, George. It would take a very enterprising team with visionary leadership to take SDCs to the next level. Is there a chance this model replaces the fabless one on grand scale?
I think this has been true for over five years now, nearly ten, and it is (almost) the death of the fabless semiconductor company. Fifteen years ago, I had numerous clients making SoCs for numerous markets - printers, smart phones, etc. All have gone out of business, and so far as I know there aren't new ones. Why? Because it costs north of $10 million to produce a new SoC, even at the larger sizes, like 90 nm. Worse, it takes 18 months. A company is therefore faced with the challenge of gambling a BIG pile of money on what the market will demand 18 months or more down the road. That's tough to do. Worse, though, is that all the SoC companies actually had very little hardware value-add. Every design had a ARM core, some RAM, a graphics controller, a network interface, and the usual assortment of serial I/O, from UART to USB to SPI, etc. I quite literally recycled block diagrams for the data sheets of several clients. CPUs and most peripherals are commodities today; any value-add is in software. For us hardware guys, this is rather depressing. The problem is compounded by the fact that a fabless company always has, in effect, a double margin hit - their own margin plus that of the foundry. If the market is truly large, a major vendor such as TI or Intel can afford to buy market share with price. The ideas suggested below for a mixed device - one with an ARM, the usual peripherals, and a chunk of FPGA, is likely to be the future. Anyone doing it yet? Side note: if you're a foundry, and there are no fabless chip companies, how do you make money?
I agree. While standard SOCs are still great for mass scale products, they don't work well for small volume, or experimental or time to market products. But FPGAs are not perfect either. We really need more companies making software defined ASSPs - that is an ASSP with a large pool of configurable logic. Sure the FPGA vendors have a few, but its not that rich a portfolio. I can even see approaches like that working within a company. An in house ASIC that is adaptable to many use cases.