How SystemVerilog Interface Classes Allow Multiple Inheritance

How SystemVerilog Interface Classes Allow Multiple Inheritance

Have you heard about SystemVerilog interface classes (IFC from now on)?

I admit I didn't, until a few months ago. Recent project made me research how to approach a certain verification problem, and in doing so, I discovered IFC.

In this article, my goal is to briefly explain what are IFC and how they can be useful.


Understanding IFC with dogs, cats, and birds

I'm going to use well-known example here, the one which is often used to explain inherritance and polymorphism. You guessed right - good old domestic animals example.

Most of us met inheritance through this simple example. There is an animal class with a make_sound method. Inherrited classes are dog, cat and bird.

Here is well known example that is always used to illustrate inherritance and polymorphism:

class animal;
   virtual function make_sound();
      $display("Generic animal sound");      
   endfunction
endclass

class dog extends animal;
   virtual function make_sound();
      $display("WOOF");      
   endfunction
endclass

class cat extends animal;
   virtual function make_sound();
      $display("MEOW");      
   endfunction
endclass

class bird extends animal;
   virtual function make_sound();
      $display("CHIRP");      
   endfunction
endclass

module test();
   initial begin
      animal a;
      dog d = new();
      cat c = new();
      bird b = new();

      d.make_sound(); //WOOF
      c.make_sound(); //MEOW
      b.make_sound(); //CHIRP

      a = d;
      a.make_sound(); //WOOF
   end
endmodule        

Now, what happens when you want to add duck to your home zoo? Duck can fly() and swim(). We can add these to the base class, but the inheritance tree starts to get messy. Many child classes many not use these methods at all.

This is where IFC come into play. In a way, they say that certain class "can do" something, without locking it to certain hierarchy tree.

Let's see a piece of code to understand how it works.

We first declare interface classes:

interface class talker;
   pure virtual function void make_sound();
endclass

interface class flyer;
   pure virtual function void take_off();
endclass

interface class swimmer;
   pure virtual function void swim();
endclass        

Note the pure virtual methods declaration.

Then we have our "regular" classes which impelement required interfaces:

class bird implements talker, flyer;
   virtual function void make_sound();
      $display("CHIRP"); 
   endfunction

   virtual function void take_off();  
      $display("FLY");
  endfunction
endclass

class dog implements talker;
    virtual function void make_sound(); 
      $display("WOOF"); 
   endfunction
endclass

class duck implements talker, flyer, swimmer;
   virtual function void make_sound(); 
     $display("QUACK"); 
  endfunction

   virtual function void take_off();   
     $display("FLAP FLAP"); 
  endfunction

   virtual function void swim();       
     $display("SWIM"); 
  endfunction
endclass        

Test:

module test();
   initial begin

      dog d = new();
      bird b = new();
      duck du = new();

      d.make_sound(); //WOOF
      b.make_sound(); //CHIRP

      b.take_off(); //FLY
      du.take_off(); //FLAP FLAP
      

   end
endmodule        

Each class can simply implement what they need from different interfaces.


Conclusion

Why is this important? Sometimes in our testbenches we don't have clear line of inherritance. Instead, we want our classes to be able to "do" multiple things. Inherritance is still good and interface classes do not replace it. They complement it.

Note that here I have descirbed only one small feature of interface classes - multiple inherritance. They are in fact much more powerful. One usage is to add dynamic connections similar to TLMs (TLMs are static).

I encourage you to explore DVCon articles and search online for more on this topic. It's quite interesting and learnig it will allow you to nicely complement and polish your testbenches

Sad story about analysis ports

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