Choosing Ceramic Capacitors for Decoupling Applications

🙄 Debunking a Decades-Old Myth: The "3 Capacitor Values" Rule For years, we've followed the "rule" of placing three different decoupling capacitor values: 0.1µF, 0.01µF, 0.001µF or more commonly 10µF/1µF /0.1µF on each power pin to cover a broad frequency range. The idea was simple: larger caps handle low frequencies, smaller ones take care of high frequencies. This guideline appears in countless schematics and datasheets. But as explained in this eye-opening article by Eric Bogatin, Larry Smith, and Steven Sandler ("The Myth of Three Capacitor Values" – Signal Integrity Journal), this is largely a myth in modern designs. The rule originated in the through-hole era, where smaller-value ceramic disk capacitors had shorter leads → lower ESL→ better high-frequency performance. With today's MLCCs, dominant for >20 years, capacitance is decoupled from package size. A 10µF and a 0.1µF MLCC in the same footprint have nearly identical ESL (often <1nH with good layout). Result? High-frequency performance is dominated by mounting inductance (loop area, via placement, routing), not the capacitance value. Using widely spaced values often creates unwanted parallel resonance peaks in the impedance profile potentially worsening noise! Simulations show that multiple identical higher-value MLCCs (e.g., several 10µF) can yield a flatter, better impedance curve. So how should we select capacitor values today? There is no universal magic set of three values. The right answer is: Prioritize lowest possible ESL through smart placement (as close as possible, short power/ground paths, vias-in-pad if needed). For single-cap situations (low-current pins): Use the highest capacitance in the smallest practical package e.g., 1–10µF in 0402/0603. For multiples: Consider identical values to avoid resonances, or model the full PDN. Always aim for a flat, low target impedance profile across the needed frequency range, this requires system-level analysis (VRM, package, die effects), not blind rules. Bottom line: Stop blindly applying 50-year-old guidelines. Analyze your PDN, optimize layout for low inductance, and test thoroughly. 🤔 What outdated "rules" have you recently questioned in your designs? #PowerIntegrity #DecouplingCapacitors #PCBDesign #SignalIntegrity

You're switching at 2.2MHz with a standard input cap bank: 22µF, 1µF, 100nF, 10nF ceramic. The fundamental is clean. But the 2nd harmonic at 4.4MHz is failing conducted EMI by 10dB. You add more caps and it even gets worse. What's going on? Every ceramic cap has a self-resonant frequency where its impedance hits minimum. Below SRF it's capacitive. Above SRF it's inductive. When you parallel two caps, the frequency band where one is inductive and the next is capacitive creates an anti-resonance peak where the combined impedance actually increases. With decade-spaced values (22µF, 1µF, 100nF, 10nF), the SRFs fall at 1.3MHz, 7.1MHz, 25MHz, and 92MHz. None of them are on your harmonics. Worse, the anti-resonance between the 22µF and 1µF lands at 4.5MHz, right on your 2nd harmonic. Your filter is amplifying the one frequency you need it to suppress. The fix isn't adding more caps. It's choosing values so the SRFs land on the harmonics you need to filter. SRF = 1/(2π√(C×ESL)). For a given package with known ESL, you can work backwards from your target frequency to the capacitance value that resonates there. For a 2.2MHz converter, that gives you 6.8µF, 2.7µF, 1.2µF, and 820nF, each targeting the 1st through 4th harmonics. The result is the impedance at the 2nd harmonic drops from 53mΩ to 4mΩ. A 13× improvement from changing four component values. Same package sizes, same PCB footprint, same BOM cost. Stop picking decade values for your input caps. Design the SRFs to land on your harmonics. #PowerElectronics #EMC #CapacitorSelection

🎯 “Decoupling in High-Frequency Analog — When Cap Size, Placement & Parasitics Start to Matter” At low frequencies, decoupling is a checklist item: 🔹 Add a 0.1 µF cap near the supply 🔹 Done. But in high-frequency analog — VCOs, LNAs, high-speed ADCs — decoupling becomes a discipline. Because what used to be a humble capacitor… now becomes a source of resonance, noise, and failure — if not handled right. --- ⚡ Why High-Frequency Decoupling Is Tricky In the GHz domain: Capacitors are no longer “ideal” — parasitic inductance (ESL) and resistance (ESR) dominate PCB traces behave like transmission lines Supply noise becomes phase noise “Short distances” become effective antennas > A poor decoupling strategy won't just add ripple — it will kill your analog performance silently and unpredictably. --- 🛠️ Smart Decoupling Strategy 🔹 1. Use Capacitors in Parallel — Targeting Different Frequency Bands Use a mix of capacitor values in parallel, each tuned for a different noise range: 10 µF bulk capacitors help stabilize supply at low frequencies (below 1 MHz) 0.1 µF general-purpose caps are effective in the 10–50 MHz range 1 nF capacitors are useful around 100–500 MHz for smoothing fast edges 100 pF RF decoupling caps are effective at GHz frequencies and beyond This technique ensures your power line is clean across the entire noise spectrum. --- 🔹 2. Placement: Loop Area is the Real Enemy The capacitor’s value doesn’t matter much if placed poorly. Keep the current loop area as small as possible Use short, wide traces Prefer vias-in-pad or very close stitching vias Place the cap right next to the supply pin > Think of each capacitor as a fire extinguisher — Useless if it’s down the hall during a fire at your desk. --- 🔹 3. Know Your Parasitics Real-world capacitors have more than capacitance. They come with Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL): High ESR adds voltage ripple during current transients High ESL limits the cap’s effectiveness at high frequencies Beyond the self-resonant frequency, the capacitor starts acting like an inductor 💡 For example, a 0.1 µF capacitor with 1 nH ESL loses effectiveness beyond ~160 MHz. --- 🔹 4. Avoid Unintended Resonance Multiple capacitors in parallel can unintentionally create LC tank circuits, leading to impedance spikes — not dips. To flatten the response: Add small series resistors (~1–2 Ω) Use ferrite beads between blocks Avoid clustering too many identical cap values in one place --- 🔹 5. Ground and Power Planes Matter Don’t just focus on VDD — the return path (ground) is equally critical: Use solid, low-impedance ground planes Don’t let digital return currents share the analog ground Use stitched grounds and separate analog/digital regions carefully > Clean VDD with a noisy GND still leads to performance loss. #AnalogDesign #Decoupling #CapacitorSelection #PowerIntegrity #PDN #RFDesign #GHzCircuits

𝐃𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐃𝐞𝐦𝐲𝐬𝐭𝐢𝐟𝐢𝐞𝐝 𝐏𝐚𝐫𝐭 5: 𝐀 𝐦𝐮𝐜𝐡 𝐛𝐞𝐭𝐭𝐞𝐫 𝐝𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐬𝐭𝐫𝐚𝐭𝐞𝐠𝐲! In parts one to four of this series, we went through the capacitor model, simulation methods, Q factor, and a very common decoupling network that turns out to work very badly. In this part, we’re going to look at superior solutions. 1️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐫𝐬𝐭 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a 𝐝𝐞𝐜𝐨𝐮𝐩𝐥𝐢𝐧𝐠 𝐧𝐞𝐭𝐰𝐨𝐫𝐤 with a combination of 4 𝐡𝐢𝐠𝐡-𝐯𝐚𝐥𝐮𝐞 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫𝐬 and a test board used to measure it. Why 4 high value capacitors? 💡 The high capacitance kills the Q factor. 💡 Because they all have the same value, they all transition from capacitive to inductive (see 𝐩𝐚𝐫𝐭 1 in the series), which means they don’t create extra parallel resonances! You’ll just get a 𝐬𝐢𝐧𝐠𝐥𝐞 𝐝𝐞𝐞𝐩 𝐬𝐞𝐫𝐢𝐞𝐬 𝐫𝐞𝐬𝐨𝐧𝐚𝐧𝐜𝐞. These don’t “hurt” since they don’t cause supply ringing when exposed to a load current pulse. 💡 This solution is also 𝐜𝐡𝐞𝐚𝐩𝐞𝐫 since you only need 𝐨𝐧𝐞 𝐜𝐚𝐩𝐚𝐜𝐢𝐭𝐨𝐫 𝐯𝐚𝐥𝐮𝐞 instead of three or four, and your production becomes easier with a 𝐬𝐦𝐚𝐥𝐥𝐞𝐫 𝐁𝐎𝐌 (Bill of Materials). You may wonder: why four? Can I not use a single 100nF capacitor? And you would be right, this will solve the parallel resonance problem as well! Putting four in parallel does have the advantage of creating a lower RF impedance since you now have four parallel paths to decouple. Four larger capacitors in parallel also increase the local energy storage, making the network more resilient for load pulses. 2️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐬𝐞𝐜𝐨𝐧𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a simulation schematic of this network in a 50-Ohm measurement system (see earlier parts in this series for more details). 3️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐭𝐡𝐢𝐫𝐝 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see the simulation result and a measurement result. They are quite close! The RF suppression is slightly better for the real circuit due to the use of first-order RLC models, which have some limitations. 4️⃣ 𝐓𝐡𝐞 𝐟𝐨𝐮𝐫𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞 shows my measurement setup: A NanoVNA connected to a laptop running NanoVNAsaver. 5️⃣ 𝐈𝐧 𝐭𝐡𝐞 𝐟𝐢𝐟𝐭𝐡 𝐩𝐢𝐜𝐭𝐮𝐫𝐞, you see a simulation of how these networks behave when hit with a load current pulse. The classic decoupling approach shows ringing. The 4×100nF approach does not ring at all and the voltage drops less, due to the higher total capacitance, making it much 𝐦𝐨𝐫𝐞 𝐫𝐨𝐛𝐮𝐬𝐭 𝐟𝐨𝐫 𝐥𝐨𝐚𝐝 𝐩𝐮𝐥𝐬𝐞𝐬. It can store more energy. 👉 In the next part, I’m going to show you the ultimate decoupling strategy. 🎬 If you can’t wait for that, check this video: https://lnkd.in/eVBtD_c9 🎓 𝐈 𝐚𝐥𝐬𝐨 𝐡𝐚𝐯𝐞 𝐚 𝐜𝐨𝐮𝐫𝐬𝐞 — you can watch a free module and get a free checklist here: https://lnkd.in/ews6cwQm Best regards and happy designing, Hans Rosenberg