What a generated clock actually is?
Most engineers think STA timing closure starts with create_clock.
It doesn't. That's just where it gets comfortable.
The real complexity begins the moment your clock enters the fabric of the design and architecture starts reshaping it.
Here is what every VLSI engineer should have locked in their mental model:
What a generated clock actually is?
"A generated clock is a clock derived from a master clock."
— But that one sentence hides enormous depth.
It is a declaration of:
→ WHERE the clock originates (the master pin via -source)
→ HOW it is transformed (-divide_by, -multiply_by, -edges, -invert)
→ WHAT waveform actually reaches downstream flops
→ HOW STA should propagate timing through the entire clock network
And critically, the origin of a generated clock remains at the MASTER clock definition point, not at the generated clock pin. This means source latency is automatically included. Define a new master clock instead, and you lose this. You now manually own every latency calculation.
5 scenarios where wrong definitions break your signoff
Here's what generated clocks actually mean, with every circuit and waveform you need to see it clearly.
1. DIVIDER FLOP OUTPUTS:
STA has no idea your divide-by-2 flop changed the period to 20ns.
You must tell it with:
create_generated_clock -name CLKPDIV2 -source UPLL0/CLKOUT -divide_by 2 [get_pins UFF0/Q]
Miss this → wrong setup/hold budgets on every downstream path.
Concept 1 — divide-by-2 generated clock
Circuit: Master clock → Flip-flop divider → Generated clock
Waveforms: CLKP (10 ns) → CLKPDIV2 (20 ns)
Why this matters?
Without the generated clock definition, STA assumes the period at UFF0/Q is still 10 ns. Every setup/hold budget downstream is computed on the wrong period.
"The divide-by happens in silicon, STA is blind to it unless you describe it in SDC."
2. CLOCK GATING CELL OUTPUTS:
When SYS_CLK is gated by a flop, the output of the AND cell(UAND1) needs a generated clock, identical to the source, divide_by 1.i.e., We need to define a generated clock on the output pin of the UAND1 in our SDC.
Without it → STA either ignores the gated domain or applies incorrect latency.
Concept 2 — clock gating cell output
Let's consider a circuit where we have clock named SYS_CLK gated by a flip-flop enable → AND cell → CORE_CLK
Waveforms: gated clock has same period, but can be blocked
Definitions/ SDC Commands:
create_clock 0.1 [get_ports SYS_CLK]
create_generated_clock -name CORE_CLK -divide_by 1 -source SYS_CLK [get_pins UAND1/Z]
Without this: STA may not propagate timing through UAND1/Z at all. It won't see CORE_CLK as a clock. All setup/hold checks on the core logic become unconstrained. No violation reported = false confidence.
3. MUX-SELECTED CLOCKS
Two clocks feeding a mux → if select is unconstrained, both propagate, which is false.
STA will analyze false cross-domain paths (e.g., TCLK to TCLKDIV5).
Result → false failures, wasted ECOs, wrong confidence.
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⚠ If CLK_SELECT is unconstrained, STA propagates BOTH clocks through the MUX.
It then analyzes timing paths from TCLK-driven flops to TCLKDIV5-driven flops -> the paths that can NEVER physically occur. This causes false setup failures, wasted ECOs, and wrong slack confidence.
create_generated_clock -name TCLK_OUT -source TCLK -divide_by 1 [get_pins CLK_MUX_OUT]
Also set_clock_group on those 2 clocks which are logically exclusive.
set_clock_groups -logically_exclusive -group [get_clocks TCLK] -group [get_clocks TCLKDIV5]
4. THE -INVERT TRAP
"STA will create the generated clock as specified whether it is realizable or not."
If we place -invert at the wrong point in the clock path, STA fabricates a waveform that cannot physically exist.
It still reports timing.
It still shows slack met.
But the analysis is wrong. And it will pass the signoff.
⚠ "STA will create the generated clock as specified whether it is realizable or not."
Setup timing reports PASS.
Hold timing reports PASS.
The waveform that STA analyzed does not exist.
The chip fails in silicon.
5. EDGE MANIPULATION (-edges, -edge_shift)
For non-50% duty cycle clocks or phase-shifted domains, using -edges {1 2 5} with -edge_shift is the precise tool.
Generic divide_by gets it wrong silently.
The 3-part latency model: How total clock latency accumulates from oscillator to flip-flop CK pin?
What breaks?
If you replace the generated clock with a new master clock, STA starts fresh at that point.
The master source latency is NOT automatically carried.
You must manually specify it with set_clock_latency -source.
If we miss one term and every slack number is wrong.
The -invert trap and the latency accumulation model are where production tape-outs might go wrong. Constraint sanity review is not optional at signoff.
Total clock latency to a flop clocked by a generated clock =
Source latency of MASTER clock
+ Source latency of GENERATED clock
+ Network latency of GENERATED clock
Every term matters. Especially in post-CTS signoff where source latency values are locked.
In mature SoC flows, generated clock review is a mandatory gate. The engineers who own it are the ones trusted with complex tape-outs.
The timing issues we blame on CTS, placement, or routing, let’s go look at our generated clock definitions first.
If we are building expertise here,
Let's Master these four areas in SDC:
✦ create_generated_clock — every option, every edge case
✦ set_clock_latency — source vs network, -late / -early split
✦ set_clock_groups — exclusive, asynchronous, logically exclusive
✦ Clock gating checks — set_clock_gating_check, mux handling
Master clocks define frequency.
Generated clocks define reality.
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