Visualizing Historical ADC Performance Data

In the plenary talk titled "The Future of RFIC is Digital" which I presented at the 2022 RFIC Symposium in Denver, I animated the ADC performance data set collected by Boris Murmann and his research group over the last 25 years [1], in order to help the audience visualize progress in CMOS data converters as well as to understand how designers have made tradeoffs historically, while controlling for different variables such as sample rate, process node, power dissipation, and SNDR.

FOMs and SNDR versus Fsnyq

This first video illustrates the Schreier Figure of Merit (FOMs) [2] vs sample rate (Fsnyq), process node (color bar, with diamond markers indicating finFET designs), and year of introduction, for CMOS ADC designs. The figure then pivots from FOMs to SNDR vs the same quantities, showing a steep drop-off in SNDR beyond ~2GSa at a slope of 20dB per decade, which can be attributable to jitter limits.

From the time evolution of this data, we can extract a plot of FOMs at 1Gsa versus process node:

The theoretical limit of ADC energy efficiency limits FOMs to below 192dB [3]. This graph suggest 1GSa data converters will be pushing against these limits at or before the 1.5nm node.

Jitter versus Process Node

Similarly, the next video shows SNDR vs Fsnyq over time and process node, with 10dB/decade and 20dB/decade trend lines fitted.

I used the 20dB line to back-calculate jitter versus process node, showing current designs nearing the 10fs range.

SNDR versus Power, Controlling for Process and Fsnyq

Finally, we can examine how ADC power consumption and SNDR trade against each other for designs above 1Gsa and for specific process nodes (16nm in this case), by a simple plane fit to the data. Analysis of 40, 28, and 16nm nodes results in fits with R^2 > 0.65 and this suggests that designers have encountered a trade of 0.7-0.9dB power per dB SNDR. At this time there's not enough design data at more advanced nodes for meaningful analysis.

Conclusion

I hope you find these graphs interesting and illuminating, and I look forward to others developing improved analyses. For example, the data set includes information on ADC topology, which was not studied here. It should be pointed out that the fitting performed in these various graphs is pretty basic and has clear limitations: for example, the process node name in more advanced nodes does not correspond to actual gate length (not available in the data set), despite the fact that gate lengths have indeed steadily shrunk. They also do not distinguish between improvements attributable to process versus design innovations, or digital versus analog improvements. And of course historical data is only so useful for predicting the future (such as one does in a plenary presentation). Nevertheless I hope these visualizations do provide a sense for what to expect of CMOS data converters as technology (in a broad sense, not just process) advances. If there are flaws with my interpretation of the data, I'm eager to hear your feedback, critique and perspectives.

[1] B. Murmann, "ADC Performance Survey 1997-2021," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html

[2] FOMs can be expressed in dB as SNDRdB + 10Log(Fsynq/2/Power)

[3] “Performance comparison of analog and digital circuits”, B.J.Hosticka, Proceedings of the IEEE, Vol. 73, Jan. 1985