Power Integrity using ADS

Power Integrity using ADS

The process of designing a power supply was always a challenge in making the required trade-offs between performance, reliability, time-to-market and cost, but it wasn’t always as technically complex and difficult as it is now. In the golden days of the twentieth century, most of our challenges revolved around dealing with imperfect devices and project requirements of cost and schedule when, in the final moments of a deliverable product schedule, the belated realization struck—that a power supply was required or the current one wasn’t working very well.

It’s difficult not to long for the simpler, good-old-days when mainstream power supply outputs were 12V or 5V plus or minus 10%, noise windows were measured in hundred of millivolts and currents were measured in amps or tens of amps.

Reflecting on obsolete jobs like crafting carriage wheels or manufacturing buggy whips, we analog and power engineers should be grateful for having critical skills in the modern technological ecosystem. We’re fortunate that when software skills get stale in a few years, the immutable laws of physics don’t change. For power integrity engineers, mastering the fundamentals gives us timeless skills. Regardless of fads and social trends, we can count on V = L(di/dt ) and W = 1/2Lie2 —physics will never abandon us.

Advances in technology drive increasingly strict and difficult requirements. Common power supply rails are quickly headed toward 0.5V or less. For a big CPU, GPU, ASIC, NPU, AI/ML processor or FPGA, currents are now hundreds of amps and headed higher. Transistors are switching at multi-gigahertz rates with edges at least 10X greater. For state-of-the-art designs, we’re dealing with transient currents of hundreds of amps at rates of 1000A/μSec and higher.

What drives these changing requirements?

I always think of 30kV per centimeter. Somewhere near that voltage, air breaks down and this sets a scalable limit. If we need an air gap to sustain 15kV in air, then the distance between conductors must be at least 0.5cm, and probably much less depending on moisture and contaminants. In the semiconductor world—where distances between conductors and across switches are increasingly smaller—standoff and breakdown voltages get lower and lower.

With things getting smaller and requiring equal or greater power handling at lower voltages, currents and power densities increase. We’re dissipating more and more power in smaller and smaller volumes. A big chip might have billions of individual transistors—all switching at both correlated and uncorrelated rates.

Let’s dream up an imaginary power supply and try to think of diabolical ways to break it. What would we do?

We’d require lower voltages with tighter tolerances.

We’d change the regulated voltage in operation at the system’s whim.

We’d require massive currents.

We’d ask for large current changes at very fast rates.

As time passes, we’d ask for higher and higher efficiencies and power densities.

All these things and more are happening with increasingly compressed schedules.

Overall, we should be grateful, because this work is not easy and it will be vital for the foreseeable future. Not all of our engineering colleagues have the same employment outlook.

Fortunately, there are books like the Sandler/Davis Power Integrity using ADS to help us navigate the changing design environment.