1. Problem Statement
1.1 Complexity Management
- Issue: Combining multiple UVCs increases testbench complexity, inevitable in large verification projects.
- Impact: Hard-to-debug failures, maintenance challenges, and communication bottlenecks due to poor encapsulation of UVC details.
- Goal: Encapsulate complexity to maintain project efficiency and support team members unfamiliar with all details.
1.2 Insufficient Control
- Issue: Sequences manage stimulus well for common scenarios but may restrict control over detailed UVC options, especially in subsystem/chip-level environments.
- Impact: Randomization across UVCs can produce illegal configurations without system-level constraints, requiring directed tests that slow coverage closure and risk missing bugs.
- Goal: Provide an API for fine-grained scenario control without compromising simplicity.
1.3 Insufficient Reuse
- Issue: Sequence libraries are often project-specific, coupled to design architecture, and duplicated with minor changes within a project.
- Impact: Increased complexity, maintenance burden, and lack of portability to new projects.
- Goal: Design sequences for reuse across projects and within libraries, minimizing duplication.
2. Sequence API Strategy
This section defines a strategic approach to sequence design, setting goals for test sequences, top environment sequences, and interface UVC sequences.
2.1 Test Sequences
- Definition: Top-level sequences started by uvm_test, encapsulating all constrained random stimulus.
- Goals : Complexity: Simple, manageable by users unfamiliar with testbench details. Control: Rich API for selecting system and interface-specific scenarios. Reuse: Independent of project-specific configurations, reusable across derivative projects.
2.2 Top Environment Sequences
- Definition: Mid-level sequences in the top uvm_env, interfacing between test sequences and UVC sequences.
- Goals : Complexity: Ensure legal system-wide stimulus, hide UVC details, allow step-wise constraint solving for debug. Control: Derive UVC options from test inputs, manage UVC relationships, handle system resources (e.g., register models). Reuse: Minimize UVC change impact, portable across architectures, avoid constraint duplication.
2.3 Interface UVC Sequences
- Definition: Lowest-level sequences specific to UVC protocols (e.g., AHB, PCIe).
- Goals : Complexity: Guarantee protocol-legal stimulus, manage data handling (e.g., CRC), hide encoding details. Control: Comprehensive API for legal operations and error injection. Reuse: Protocol-specific, independent of design architecture or registers.
3. Sequence Library Solutions
Implementing the Sequence API strategy, structured around encapsulation, hierarchy, and configuration/reuse.
3.1 Encapsulation Overview
- Approach: Sequences encapsulate complexity, offering control via control knobs (random fields) and derived fields, reducing user burden.
3.2 Hierarchy Guidelines
- Guideline 1: Produce legal stimulus by default.
- Guideline 2: Use class constraints for control knobs, inline constraints to pass values.
- Guideline 3: Minimize control knobs, hide derived fields.
- Guideline 4: Dedicated constraint blocks per knob for extendibility.
- Guideline 5: Use soft constraints sparingly to avoid silent overrides.
- Guideline 6: Enumerated types for knobs.
3.3 Top Environment Sequence Guidelines
- Guideline 7: Keep tests generic, independent of architecture.
- Tip: Provide random and directed sequence versions.
- Guideline 8: Use descriptor objects for complex constraints.
- Tip: Enumerate scenario control knobs (e.g., sequential/parallel data flows).
3.4 Configuration and Reuse Guidelines
- Guideline 9: Configuration objects with accessor methods for adaptability.
- Guideline 10: Utility methods for self-tuning.
3.5 Sequence Library Management
- Tip: Use typedef headers for readability.
- Tip: Messaging in pre_start()/post_start() for debug.
