HCL Data Plane Acceleration Solution

Performance expectation from data plane resources has been rapidly increasing because of traffic and device mix in telco network. With telco cloud adoption on rise, there is also a race to hog compute resources by a number of network functions. Telco network virtualization initiatives require FPGA based SmartNIC solution to fully realize the potential of virtual network functions. To meet the 5G latency, throughput, and QoS needs, almost, all of the telecom players acknowledge the need for data plane acceleration solutions, but it’s just the approach that each one of us have difference on implementation. HCL has been following an approach to offload a few of the compute intensive workloads tasks in the FPGA, collaborating with Intel. Apart from flexibility and programmability, HCL considers time to implement, solution cost, and performance efficiency in building data plane acceleration solution for various network functions. HCL data plane acceleration solution will enable effective deployment of network function at the edge that demands low power and footprint because of the resource constraints. Performance of network workloads such as SRv6, OvS, vEPC, vIMS, vRAN, vRouter, vFW, vBNG, can be improved using HCL acceleration solution.

The key points of this solution are as below:-

·      HCL solution is VNFs vendor agnostic

·      HCL reduces the cycle time of service provider to validate the performance improvement in their specific network topology

·      The service providers take the advantage of this solution to further extend other VNF acceleration program one by one

·      HCL manages the multi-vendor programs to reduce the service provider operational overhead

·      HCL to demonstrate the values with real non-sensitive and low risk traffic, if needed

HCL has demonstrated its acceleration solution on SRv6 with Intel’s first PAC with Arria 10 FPGA. By leveraging VPP plugin-based framework and offloading CPU intensive SRv6 operations on Intel’s first PAC with Arria 10 FPGA, HCL has built an optimized architecture which greatly increases the throughput and lowers latency for the data plane. RFC 2544 performance results indicates an average improvement of more than 65% in CPU cycles saving. For most common network scenarios, 2 CPU cores are saved in 4C4T configuration.

With the DP acceleration solution, HCL can engage telco directly or indirectly depending on the phase in the acceleration program. One of the key advantages working with HCL is that that HCL program is network functions vendor agnostics. HCL engagement work flow with a telco with a pilot by getting the data plane acceleration goal for a specific networking function and demonstrate the quantifiable performance values through its FPGA based solution. We can start showing the value of a networking function to begin with and then scale with other workloads.

HCL is committed to make the telco deployment seamless and optimized through other solutions IPs ranging from edge, core, and cloud infrastructure to local and national DCs. HCL goals are to build telco focused solutions to guarantee the SLAs, to boost spectrum capacity, and to enhance customers experience.