AMD’s Post

Open ecosystems and ROCm acceleration are exactly what the HPC and EDA communities need more of. AMD's continued investment in ROCm usability and libraries directly shapes how design teams think about heterogeneous compute for simulation and verification workloads. The emphasis on speed as the moat is spot-on — in EDA tooling, runtime performance is a first-order productivity metric that compounds across every design iteration. Looking forward to hearing more about the software stack at AI DevDay. #ROCm #EDA #HPC

This is about owning the software layer to unlock hardware performance. ROCm's push + open ecosystem strategy targets developer accessibility and workload portability across accelerators. If they can match performance while reducing friction, software velocity becomes the real moat.

I built a photonic logic chip where interference fringes ARE logic gates. No silicon. No etching. Computation leaves no physical trace. 5.289 mW @ 50 GHz 400 GIPS (8-core) 28 verified claims 🧵 Thread below 👇 The core idea came from watching sunlight reflect on water. Light flickering on/off = logic states switching. What if interference fringes were logic gates? That question became 10 versions of verified photonic computing architecture. Key breakthrough: angle-as-logic. Light beam angle θ = logical state Vector sum of beams = AND/OR gate Phase inversion = NOT gate No transistors. Pure geometry. Security advantage nobody else has: Computation IS the light field. When it ends — nothing remains. No side-channel attacks. No audit trail. Physically ephemeral. 7/8 cores compromised = 0% information leakage. CERN Zenodo DOI published: 10.5281/zenodo.19801651 GitHub: github.com/maomaoati-coder/Photonic-Logic-Chip- 28 claims. SHA256 chain. FDTD simulation. Standard draft PLC-STD-001. Open for licensing / collaboration / feedback. maomaoati@gmail.com

Anush, caught the TBPN segment. While ROCm is winning on speed, the 'Standard' for the next wave will be defined by Deterministic Reliability. I've finalized DESE-DEE, a finished primitive for deterministic state governance. It's a silicon-ready architecture [Doc C11] that provides the bit-perfect Infrastructure Attestation (IAR) and KV-Cache Governance that AMD needs to secure its lead in the Enterprise ISV space. I’ve hosted a DCIE (Guided Tour) specifically for the reasoning models of architects focused on ROCm acceleration.

"Speed is the moat" is a bold statement, but AMD has consistently backed it up. The software stack conversation often gets overshadowed by hardware specs, but it is actually what determines how fast developers can build and ship on top of AMD.

Speed as the moat in AI infrastructure, that is not just a competitive advantage. It is the only one that compounds. Open ecosystems and ROCm acceleration democratizing AI compute means the next wave won't be built exclusively on proprietary stacks. The developers who build on open infrastructure today will define what is possible for everyone tomorrow. 🌏

Software is really becoming the key differentiator in AI performance. Excited to see how AMD continues pushing the ROCm ecosystem forward.

Excited