David Garnett

Texas Instruments announced plans to invest $60 billion for new facilities in Utah and Texas, in an effort to reshore semiconductor chip production. Texas Instruments did not give a timeline for when the investments will be made. Fidelis Companies https://lnkd.in/gR8kTWWt

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Intel will start to lay off its fab personnel at its Silicon Forest campus in Oregon from the middle of July. The first round will conclude by the end of that month, but the company says it may perform another round of layoffs if it deems necessary. https://lnkd.in/gq7bQnmG

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We obsess over shaving microamps in firmware while ignoring the real power vampire: power integrity collapse. After debugging three field failures in battery-powered medical devices, I’ve learned the hard way: Your firmware optimizations mean nothing if your power delivery network (PDN) is lying to you. Case Study 1: A "5µA sleep mode" IoT sensor kept dying overnight. Root cause? A 4.7µF ceramic capacitor’s resonant frequency (150MHz) coincided with the DC-DC converter’s switching frequency. Result: 200mA current spikes every 10ms, draining the battery in 6 hours instead of 6 months. Case Study 2: An automotive ECU resetting during cold starts. Issue? Voltage droop (-1.2V below nominal) when the fuel injector fired. The 3.3V rail dipped to 1.8V for 500ns, just enough to corrupt the RTC’s shadow registers. Why We Ignore PDN: Toolchain Blindness: Most embedded IDEs can’t simulate PDN impedance. We optimize code in a vacuum. Component Myopia: We select MCUs for "low power specs" but ignore that 80% of power issues stem from passive components. Frequency Illusion: We assume DC-DC converters "just work" without checking: Control loop stability (phase margin <45° = oscillations) Output capacitor ESR (too low = ringing; too high = ripple) Layout inductance (via stubs adding 2nH = 20mV overshoot) The Fix: PDN-First Design Step 1: Simulate PDN impedance (e.g., Keysight ADS) from DC to 1GHz. Target: <0.1Ω up to 50MHz. Step 2: Use mixed capacitor types: Bulk electrolytics (100µF+) for low-frequency stability X7R ceramics (1-10µF) for mid-frequency decoupling NP0/C0G (100nF) for high-frequency noise (>100MHz) Step 3: Layout rules: Place decoupling caps <3mm from MCU power pins Use 20mil+ power traces (reduce inductance by 40%) Split ground planes? NO. Use solid ground under switching components. The Ugly Truth: Most "low-power" designs fail because we treat power as an electrical problem, not a system-level physics problem. Your firmware’s sleep mode is irrelevant if your PDN is a noise generator. Question: What’s your worst power integrity horror story? Bonus points if it involved a capacitor resonance or ground bounce. #PowerIntegrity #EmbeddedDesign #PDN #EMI #Hardware

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On this day in Telcom history. 1947 – Invention of the Transistor On December 23, 1947, John Bardeen, Walter Brattain, and William Shockley at Bell Telephone Laboratories demonstrated the first solid-state transistor, a tiny semiconductor device that could amplify and switch electronic signals. This invention revolutionized electronics and laid the foundation for modern computers, mobile phones, and all digital communications technology. #telecom #history #movingmountains #letsgo

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TSMC's Arizona facility has successfully commenced production, manufacturing its first batch of chips, including NVIDIA's Blackwell AI GPUs, Apple's iPhone processors, and AMD's fifth-generation EPYC data center processors, with 20,000 wafers already produced for these key customers. While these N4 process chips are currently shipped to Taiwan for advanced packaging due to existing bottlenecks, TSMC is actively working with Amkor to establish packaging capabilities in the US and plans to expand its CoWoS packaging capacity significantly, aiming for future production of 3nm and 2nm chips and eventual on-site packaging to streamline the supply chain. #TSMC #Foundry #Arizona #Chips #Semiconductors #ChipManufacturing #NVIDIA #Apple #AMD #AIchips #SupplyChain #TechNews #MadeInUSA #Innovation #TechnologyNews https://lnkd.in/dK7jnxe7

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Great to see Chad Steider featured in The Volt Post talking about how Silicon Labs Series 3 platforms paired with Zephyr RTOS are making Matter certification more manageable for multi-protocol gateways. As standards evolve, having a stable, upstream RTOS foundation helps teams reduce rework, stay aligned, and scale with confidence across industrial applications.

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