Chetan Fegade

1/2 (2nd one in comments) : As HW systems architects, we should invariably be familiar with the Firmware(FW usually in Layer1&2 of OSI)/Middleware (MW - usually in Layer 3 & above but not application layer which uses these functions) functions that interact with the underlying hardware so the sw/hw interaction is efficient and the underlying hardware is 100% utilized. One such low-level MW functions I really appreciate are libibverbs (Infiniband verbs for RDMA) - which have stood the test of time and are used by high-level MW functions interfacing with the applications. Some of such high-level MWs are NCCL (Nvidia Collective Communications Library), openMPI (Message Passing Interfacing for distributed memory model among the servers in the DC/cloud) and openSHMEM (SHared MEMory for shared memory model among the servers in the DC/cloud). I want to bring a few points to your attention though its known wisdom for the people breathing in RDMA day in & day out :: trust me I know a few 😀 !! RDMA's 'libibverbs' has one-way functions of RDMA write and read (for shared memory model) and two-way functions of RDMA send and receive (for distributed memory model). As the name suggests, one-way functions ensure that the receiver server is not involved in the data transfer, whereas two-way functions involve both transmitting host and the receiving host during the data transfer. It gets more interesting when we observe the alternate names of one-way functions as zero-copy functions and two-way functions as single-copy functions. It should make us - the HW systems architects almost insomniacs as to where the hell, this single-copy is coming from, while the RDMA is broadly supposed to achieve the zero-copy transfers 😁 !! It turns out that in RDMA two-way functions (RDMA send & receive), the data transfer occurs this way. Sender :: application layer buffer --> Kernel buffer (though stack processing is bypassed & done in NIC) --> NIC HW buffer --> data transfer over network --> Receiver :: NIC HW buffer --> Kernel buffer --> application layer buffer. The single copy (one location to another location within DRAM) that the two-way functions refer to is :: application layer buffer --> Kernel buffer on the sender side or Kernel buffer --> application layer on the receiving host side. If we avoid it, it reduces to one-way function (RDMA write & read). We might have heard of the optimization of the RDMA send & receive verbs/functions : nothing but bringing the two-way closer to one-way by directly transferring from application buffer in the DRAM to NIC's HW buffer.

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Synopsys Inc and Arm at it again! Check out our latest blog post (linked below) to learn how the two companies are working together to simplify AI chip development.

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Left Qualcomm, no customers for two years, built an 11,800 CR company. 1. After completing his master's and PhD in Electrical Engineering from Stanford University, Avneesh Agrawal joined Qualcomm. He led the semiconductor and mobile communications space there for a decade and got the big news. 👇🏻 2. He became the President of Qualcomm India and South Asia. Over four years, he was granted over 200 US patents for his work. During this time, he noticed something. 🤔 3. India faced 4,64,674 road accidents and 1.5 lakh people lost their lives. He believed that computer vision and AI could change driver safety by making roads safer through real-time intelligence. After 15 years, He left his top job. ✅ 4. He started a company with his colleague, Julian, to solve the road safety problem in Bangalore. In August 2015, Netradyne was born. 🚀 5. The idea was simple ⏩ Build a camera-first, vision-driven fleet safety solution with on-device (edge) AI. The flagship product - Driver. i, a rugged multi-lens dashcam that analysed 100% of drive time to identify risky and positive driving behaviours. He thought he had it, but he did not. 👇🏻 6. Low latency for in-cab coaching, building training data pipelines was a challenge. Moreover, convincing fleet operators to try a camera that watched drivers was another. He had to find answers or else Netradyne would not lift off. 🤔 7. He focused on anonymised analytics and Driver training programs to ensure in-cab positive reinforcement for good driving. Moreover, he split the team between the US and India to speed model training and hardware design. By 2016, it raised 108 CR led by Reliance. 💰 8. On 24th March 2017, Netradyne finally had its first commercial customer. It worked with Load One to make their drivers the safest and best-trained drivers on the road. And then customers kept coming - Stewart Transport, General Motors and Bryan Truck Line. By 2018, it raised 148 CR from Microsoft and Reliance. 💸 9. With funds, Avneesh focused on dynamic 3D/HD mapping and packaged underwriting data for insurance companies. By 2021, it had grown to support over 1000 fleets, including Titan Freight Systems and Ace Endico and crossed 1 billion driving miles. In 2021, it raised 1120 CR from Softbank. 📈 10. As it launched Driver.i one, a professional-grade video telematics device in 2023 and scaled to 18 billion minutes with 3000 customers across US, Canada, Mexico, Germany, UK, Australia, New Zealand, India, the big moment came on 16th January 2025.👇🏻 11. Netradyne raised 778 CR led by Point 72 Ventures at a valuation of 8328 CR. It became the first Indian unicorn of 2025. 🦄 11. Today, Netradyne has clocked over 25 billion minutes of driving data and safeguarded over 125 million drivers with an impeccable 99% accuracy of alerts. 💪 ➡️Avneesh Agarwal left his crores in salary at Qualcomm with no customers for two years to build an 11,800 CR company today. He is a man of true inspiration! 🙏 #startups #india

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🚀 Physical Design is NOT PnR. It is System-Level Convergence. Placement & Routing is just one phase. Real Physical Design is where architecture, logic, power, test, and reliability intersect before silicon tapeout. PD is not execution. PD is orchestration. It sits at the center of interdependent domains: 🔹 Synthesis – Bad constraints = bad silicon. PD inherits logic quality. 🔹 STA (Static Timing Analysis) – Timing closure is iterative, cross-corner, cross-mode, and never isolated. 🔹 DFT – Scan chains, compression logic, and test modes reshape placement, routing, and congestion. 🔹 LEC – Every ECO must preserve logical intent across iterations. 🔹 Physical Verification (PV) – DRC/LVS/ERC define manufacturability. No clean PV, no tapeout. 🔹 UPF (Unified Power Format) – Multi-voltage domains dictate floorplan architecture. 🔹 Low Power Verification (VCLP) – Isolation, retention, level shifters affect both timing and area. 🔹 EMIR (Electromigration & IR Drop) – Power integrity determines long-term silicon reliability. 🔹 Full-Chip Timing – Block closure means nothing if top-level integration fails. A true PD engineer thinks beyond tools. They understand: ✔ Power grid impacts IR, EMIR, and timing margins ✔ DFT reshapes congestion and clock balance ✔ ECO loops affect LEC and STA simultaneously ✔ UPF decisions ripple into routing and CTS ✔ Timing, power, area, and reliability are always in conflict. Physical Design is not a backend step. It is the control center of SoC implementation. The best PD engineers don’t just fix violations — They anticipate cross-domain impact before it happens. #PhysicalDesign #SoC #STA #UPF #DFT #EMIR #Semiconductor #VLSI #ChipDesign

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OpenAI has signed collaborations and partnerships with Broadcom, Nvidia and AMD to deploy compute capacity for specialised needs with each. Broadcom and Nvidia partnerships will deploy 10 GW each while the AMD collaboration will add 6 GW. For a perspective of scale, by various estimates the current deployed capacity at OpenAI is estimated to be between 2-3 gigawatts A few reflections as to why these partnerships are important : 1) AI’s next breakthroughs are as much about hardware as algorithms. Building frontier models requires hyperscale compute, custom silicon and deep co-design between hardware and software teams. 2) Infrastructure is the new competitive edge. As models grow, the bottleneck isn’t ideas — it’s the ability to manufacture, optimize and deploy enough compute to support them. Companies need to understand this stack end-to-end 3) Collaboration is the only way to scale. The future of AI will be built by ecosystems: researchers, chipmakers, cloud providers, and builders working in sync. 4) AGI is a systems challenge. It’s not just about smarter models — it’s nexessarily about rethinking the entire supply chain of compute, from wafers to data centers. #AGI #Nvidia #Broadcom #OpenAI #AIacceleration

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