Vinayak Dangui

Backhaul links need extra resiliency against failures and also unexpected increase in network traffic. In this work we benefit from both satellite and optical links to support resiliency using ML for packet scheduling. Very successful implementation work on a real testbed by our Ms student Aleksandar Yonchev ! This is a great example of our collaboration with Fraunhofer, special thanks to Ramona Modroiu and Marius Corici for driving this work.

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Excited to share my new paper, “Unlocking the Potential of Co-Packaged Optics in AI and HPC: Opportunities and Challenges,” now published on IEEE Xplore (Early Access) and appearing in the February 2026 issue of IEEE Communications Magazine. In this paper, I explore how Co-Packaged Optics (CPO) can unlock the next wave of bandwidth, energy efficiency, and scalability for AI and HPC infrastructure—along with the practical challenges for real-world deployment. https://lnkd.in/g5AdecA2 #IEEE #IEEECommunicationsMagazine #IEEEXplore #AIInfrastructure #AIatScale #OpticalInterconnects #CoPackagedOptics #CPO #SiliconPhotonics #OpticalInterconnects #HPC #DataCenterNetworking #HighBandwidth #LowLatency #EnergyEfficiency #FutureNetworks #AristaNetworks

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Excited to Teach Again at UCSC Silicon Valley Extension. As high-speed design challenges grow more complex, understanding signal and power integrity isn’t optional — it’s essential. I’m teaching "Comprehensive Signal and Power Integrity for High-Speed Digital Systems" at UC Santa Cruz Silicon Valley Extension — a practical, in-depth course designed for working professionals who want to upskill or refresh their knowledge in high-speed PCB and system design. We go beyond theory to explore: ✅ Advanced SI/PI concepts ✅ Design and simulation techniques ✅ Common pitfalls in real-world systems ✅ Tools and workflows used by leading engineers If you're looking to strengthen your hardware design expertise, this course is for you. Learn more or enroll here: https://lnkd.in/gfA4_dW5 Let’s keep pushing the limits of performance — one signal at a time. #SignalIntegrity #PowerIntegrity #HighSpeedDesign #HardwareEngineering #UCSCExtension #PCBDesign

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❓ Do you believe Materials Science is everywhere? 10 years ago, a UC Berkeley materials science undergrad joined our lab. After a month reviewing corrosion papers, he quit — and went to a coding bootcamp. That moment stayed with me. Because hard science takes tremendous efforts and patience, progress rarely happens overnight. But when it does, it changes the world. Take Materials Science as an example, I would believe it is, quite literally, everywhere. From quantum materials to polymers, semiconductors, and beyond — Materials Science shapes the world we live in. And yet, its quiet brilliance often goes unseen. Let’s make this a live discussion, instead of chatting with ChatGPT... 👇 To all brilliant experts, please share one material and one application you know well or you are creating — in one sentence. I will gather them, to learn and for fun! A possible format: Application - Material + Core Function (highlight your company if you like). ➔ F-35 Fighter Jet – Radar-absorbent carbon/polymer composites that hide jet from radar (Lockheed Martin) ➔ Solar Cell – Perovskite film converting sunlight into electricity. ➔ Golden Gate Bridge – Zinc-rich primer shielding steel from salty fog. ➔ Sunscreen – Titanium oxide nanoparticles reflecting UV rays. ♻️ Friends, please repost to help gather more inputs and insights! #MaterialsScience #AdvancedMaterials #HardTech #Research P.S. Why this post? To remind us all that, in the era of AI, more people start replying on AI, yes, AI can certainly help, but human still need think and create harder (even slowly), which is vital for humankind evolution. Respect to Dr. Hitoshi Nakamura, check and learn about his battery experiments, you will know!

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Why Optical "Signal-to-Noise Ratio" is Your True Metric. Last week, we talked about Gray vs. Coherent optics. Now, let's dive into one of the most critical concepts that determines if your high-speed link will actually work: Signal-to-Noise Ratio (SNR). You can think of SNR as the difference between having a clear conversation in a quiet room versus shouting to be heard at a loud concert. What is Signal-to-Noise Ratio (SNR)? In simple terms, SNR measures the strength of your desired data signal compared to the level of unwanted background noise. *  High SNR: A strong, clear signal with little noise. Your data arrives perfectly. *  Low SNR: A weak signal drowning in noise. This causes errors, slow speeds, and dropped connections. The Bottom Line: Stop thinking only about speed. Start thinking about quality. A link with a high SNR is a fast, robust, and reliable link. A link with a low SNR is a ticking time bomb. When designing or buying optical solutions, always ask: "What is the operating SNR and what is the margin?" The answer will tell you everything about its true performance.

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I was honored to deliver a keynote at this year’s Marconi Society event today at UCLA. I opened with how control (AI), compute, and connectivity technologies each began in the 1980s as monolithic, centralized, and specialized silos, gradually evolving over decades toward distributed, composable fabrics. Today, they are undergoing a deeper transformation toward “distributed convergence,” where these three layers increasingly operate as a "distributed, composable, integrated, and intelligent fabric". Control (AI/ML): symbolic, rule-based AI → neural networks → deep learning → foundational models/LLMs → multi-agent systems Compute: mainframes → PCs → client/server → virtualization → central cloud → distributed cloud (edge) Connectivity: 1G–2G (circuit-switched) → 3G (hybrid) → 4G (packet-switched) → 5G (cloud-native) → toward 6G (AI-native) The next decade will be defined by distributed convergence, where control (AI), compute, and connectivity function as one cohesive system. This is the essence of the AI-native era. Building on this foundation, I reflected on the connectivity progression: We advanced from circuit-switched 2G, to IP-native 4G that unified transport for voice, video, and data, and then to cloud-native 5G, which transformed networks into programmable platforms for distributed workloads. We are now entering the AI-native era, where a new class of devices and applications demands a new class of networks, aligned to the dominant unit of computation: first packets, then workloads, now agents. This set the stage for the architectural continuum I discussed: - Packets move bits - Workloads run services - Agents pursue goals These layers are additive, not replacements. AI-native systems continue to rely on packet-switched substrates and cloud-native orchestration, while adding agentic and semantic capabilities on top. I framed this evolution as a progression from programmability → orchestrability → autonomy → sustainability, guided by new architectural constructs for AI-native networks , including a dual-stack model: today’s syntactic Internet alongside an emerging semantic Internet. My sincere thanks to my colleague, Sheryl Genco, Ph.D. and the Marconi Society for the invitation and for its leadership in bringing the community together to advance the future of connectivity for societal impact.

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One possibility for justifying Marvell Technology’s purchase of Celestial AI is that it might result in what would apparently be the start of renegotiations by Softbank Group to buy out the former, although in fibeReality’s opinion, by itself, it would not necessarily be an endorsement of such a judgement by the Japanese investment holding company (please see: https://lnkd.in/e3sauKHK). In fairness, Softbank may legitimately view memory as a significant XPU bottleneck, at least from a high-level perspective. However, fibeReality’s intelligence gathering points to a range of opposition by optics technologists concerning the Celestial offering, from there are substantially more elegant solutions to the memory disaggregation problem, to even a determination that disaggregated memory is unworkable. Then there is the greater power consumption involved with muxing the memory interface on the host chip up to higher rates, then going optical to the HBM stack, and next muxing down for the stack to consume the data. It would hardly be surprising if Marvell’s CEO, Matt Murphy, would currently find a potentially attractive exit to be the best option for the corporation right now, as his other recent actions to get the firm to its present status have been rather impressive, albeit undoubtedly exhausting to him personally. Broadcom remains a very formidable competitor in the overall chip sector (please see: https://lnkd.in/g9JNypg2). Broadcom maintains a dominant position with its Tomahawk and Jericho solutions, along with its strength regarding custom XPUs. Marvell remains solid with its coherent DSP and transceiver-related businesses (please see: https://lnkd.in/ehg_5NnC). It is also a principal supplier on custom XPU designs to Amazon, with the good possibility of being a backup to Broadcom at both Microsoft and Meta (while almost certainly offering lower prices at both users). Matt would further not likely wish to be around to discover the outcome of his latest investment in Celestial. fibeReality also agrees with the viewpoint that Amazon may not have compelled Marvell to assume such a costly risk, despite its endorsement in the press release that announced the deal (an arguably lukewarm statement anyway). 

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The most interesting paper I read last week, showing promising work on optical generative models that offload parts of the compute from electrons to photons. UCLA researchers demonstrated generating images by physical light propagation rather than digital computation. The approach maps diffusion model concepts to free-space optics: a shallow digital encoder converts random noise to phase patterns, then a trained diffractive surface processes light to generate images with the optical computation happening in under a nanosecond (overall speed is limited by the SLM refresh rate). This cross-pollination between fields (GenAI → Optics → GenAI) strengthens the entire research ecosystem. Moving from bits to light as the medium opens new possibilities for energy-efficient and significantly faster inference. Paper: https://lnkd.in/gC4By9Vv

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Real-Time Inference Optimization: Techniques for Edge Deployment The Real-Time Imperative In applications like autonomous vehicles, medical diagnostics, and algorithmic trading, inference latency isn’t just a metric—it’s a matter of safety and user experience. Meeting sub-100ms response times demands aggressive optimization across the entire inference stack. Core Optimization Techniques 1. Pruning: Cutting the Fat - Concept: Remove redundant weights (parameters) from neural networks. - Structured pruning: Entire channels/filters (e.g., removing 50% of ResNet50 filters → 2× speedup). - Unstructured pruning: Individual weights (sparse models, requires hardware support). - Tools: - TensorFlow Model Optimization Toolkit - PyTorch’s `torch.nn.utils.prune` - Impact: Up to 50% smaller models with <1% accuracy drop. 2. Quantization: Doing More with Less - Concept: Reduce numerical precision of weights/activations. - INT8 quantization: 4× smaller model, 2–4× faster inference (vs. FP32). - Float16 (FP16*: For GPUs with tensor cores (e.g., NVIDIA V100/A100). - Approaches: - Post-training quantization (PTQ): Fast but may lose accuracy. - Quantization-aware training (QAT): Higher accuracy, requires retraining. - Tools: - TensorRT (NVIDIA), OpenVINO (Intel), TFLite (mobile). 3. Hardware-Aware Compilation - Concept: Optimize models for specific hardware (GPUs, TPUs, CPUs). - NVIDIA TensorRT Workflow: 1. Convert model to ONNX. 2. Optimize: Fuse layers (Conv+ReLU+BN), remove unused ops. 3. Kernel Selection: Auto-tune for target GPU (Ampere vs. Turing). 4. Precision Calibration: INT8 scaling using calibration dataset. - Results: - ResNet-50: 5.7ms → 1.1ms latency on A100 (5× faster). Case Study: Autonomous Drone Navigation Challenge: Run YOLOv8 object detection at 30 FPS on NVIDIA Jetson Orin (15W power). Baseline: FP32 model → 12 FPS (too slow). Optimizations: 1. Pruning: Removed 40% of filters (structured). 2. INT8 Quantization: TensorRT with PTQ. 3. TensorRT Engine: Kernel fusion + FP16 math. Results: - 42 FPS (3.5× speedup) - Latency: 24ms (from 83ms) - Accuracy: mAP50 dropped 0.8% (79.2% → 78.4%) Toolchain Comparison | *Tool | Strengths | Use Case | | *TensorRT | Best NVIDIA GPU optimization | Edge/cloud GPUs | | *OpenVINO | CPU/Intel GPU optimizations | IoT, x86 servers | | *Apache TVM | Cross-platform (ARM, AMD, custom ASICs)| Multi-hardware fleets | | *TFLite Micro | Ultra-low memory (<100KB)| MCUs (Arduino, ESP32) | Best Practices & Trade-Offs 1. Accuracy vs. Speed: - Quantize first → prune if more speed needed. - Always validate accuracy on target data. 2. Hardware Dictates Approach: - NVIDIA GPUs: TensorRT + INT8/FP16 - CPUs: OpenVINO + INT8 - MCUs: TFLite Micro + 8-bit quantization 3. Memory vs. Latency: - Pruning reduces memory; quantization speeds compute. 4. Dynamic Shapes: - Avoid for edge deployment (use fixed batch sizes). Pro Tip: TensorRT Workflow Article will continue in comments

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