Normal Computing

The Normal team are hosting a Silicon Social during ICLR week in Rio. Join us on Sunday, April 26 from 6:30 to 8:30 PM at the Copacabana Palace for an evening with researchers, engineers, and friends of Normal who are working at the intersection of AI hardware and silicon engineering. Request an invite: https://luma.com/3ioi64wv

Chip design verification consumes up to 70% of the engineering effort on a project, and much of that effort is consumed by reading hundreds of pages of natural language specifications and manually translating them into formal, testable representations. We have been working with Fraunhofer IESE on a better approach. Today we are releasing DRAMBench, an open benchmark that measures how well AI systems can formalize JEDEC memory chip specifications into timed Petri net models. Rather than jumping from natural language to low-level verification artifacts, we introduce an intermediate formal representation. Timed Petri nets capture device states, commands, and the timing constraints between them in a compact, executable, and mathematically precise model. From that representation, you can derive SystemVerilog assertions, generate valid command sequences, and perform formal analysis. DRAMBench includes ground truth models for DDR2 through DDR4, LPDDR2 through LPDDR4, GDDR5 and GDDR6, and HBM2. It is designed as a living benchmark: as new DRAM generations emerge, previously withheld standards are released and newer ones take their place, preventing training data contamination while keeping the dataset aligned with the industry. The approach is not limited to memory. Any hardware specification that defines states, commands, and timing constraints is a candidate for the same treatment. DRAMBench and DRAMPyML are open source under Apache 2.0. The gap between natural language specifications and formal verification is one of the biggest bottlenecks in chip design, and closing it is a problem worth solving together. Read the full post: https://lnkd.in/e2ZrUsnw

Normal Computing is sponsoring ICLR 2026 in Rio de Janeiro. Our research team will be on-site presenting papers spanning thermodynamic computing, Normal's physics-based computing architecture, and the AI methods underpinning Normal EDA, our platform for silicon engineering. This work builds on our team's prior contributions to scalable probabilistic programming, ML infrastructure, and auto-formalization. Our architecture uses stochastic circuits to accelerate the sampling and inference workloads underneath diffusion and probabilistic models. On the EDA side, auto-formalization translates natural language hardware specifications into machine-checkable formal representations. Check out our published papers: https://lnkd.in/eykF6DBN Meet us at the booth: Thursday, April 23 – Saturday, April 25 9:30 AM – 5:30 PM daily Come talk to the researchers behind the work. We'll share a preview of what we're launching live at the conference. Follow along for real-time updates in the ICLR app.

Our homepage refresh is live. As Normal is partnered with more than half of the top ten by revenue semiconductor companies, we're sharing how Normal EDA enables AI-accelerated co-design for silicon engineering teams. We also share more of where we're headed, toward a new class of physics-based ASICs and the unconventional hardware and applications this approach could enable. Take a look: https://lnkd.in/eJWBZrfV

Our co-founders started Normal with a conviction. "This is not the final way that we're going to do computing. This is not the final way that we're going to design chips." In the final chapter of Inside Normal, two of our founders, Faris Sbahi and Antonio Martinez, talk about where that conviction came from. At Google X, they watched AI algorithms converge toward the equations of physics: diffusion methods, Hamiltonian Monte Carlo, processes that looked like physical systems. The intuition was that hardware should match the math it runs. Where conventional GPUs expend energy suppressing the inherent randomness of physical systems, Normal's physics-based ASICs work with those dynamics to compute more efficiently. What has gotten clearer since then is that the software and hardware are one loop. Normal EDA accelerates chip design. And we use that platform to design Normal's own silicon IP. Faris Sbahi "Normal is one of the most difficult places to work, probably in the world, frankly. You're working at the frontier of multiple fields in an effort to push and create a new field forward." But the work is important. Normal partners closely with the world's leading semiconductor companies on real production problems and has taped out the world's first thermodynamic computing chip. We're hiring across teams. Link in comments.

Normal is partnered with top semiconductor companies. What does scaling those partnerships actually look like from the inside? In Chapter 03 of Inside Normal, Craig Churchill and Johann George talk about how business and engineering work together at Normal, what the hiring bar looks like, and why this moment, where the traditional paths to scaling silicon are breaking down, creates both urgency and opportunity for a company building purpose-built AI for the problem. Johann George has co-founded six companies and says the most exciting time to join a startup is when it's scaling, because you get to define the culture. Craig Churchill came from Google X and thinks of the choice in terms of growth: 'The best fruit is always on the furthest limb of the tree.'" Both believe that the semiconductor industry's design methodology is going to change. The pressure from talent shortages, historically low first-silicon success rates, and exponentially increasing complexity guarantees it. Johann George: "Why not be part of a company that's actually part of doing the changing? You get to be part of what's happening. You get to actually change the world." We're hiring across teams. Link in comments.

What does it look like to build the product that changes how the world's most complex chips get designed? In Chapter 02 of Inside Normal, members of our product and research team talk about what it means to build Normal EDA, our purpose-built AI platform for semiconductors: where the product opportunity is, what a day actually looks like across customer deployments, product specs, demos, and engineering evaluations, and why innovation in EDA is required not just to speed up what we're already doing but to make it possible to design entirely new chip architectures. Maxwell Aifer describes why this moment matters: as the traditional paths to scaling break down, the industry needs EDA innovation not just for speed but to make unconventional chip architectures possible to design in the first place. Hanna Yip describes what happens when customers see the product for the first time. Hanna Yip: "They're seeing a process that would have normally taken them months be done in front of them in a matter of minutes." We're hiring across teams. Link in comments.

What does it look like to build a new class of computing hardware and a purpose-built AI platform for silicon engineering, at the same time? In the first chapter of Inside Normal, three members of our hardware and verification engineering team talk about that recursive relationship: why verification at Normal Computing is fundamentally different from anywhere else, how the EDA platform and the silicon program feed into each other, and what it means to work on problems that don't exist in textbooks yet. Marc Bright came from Graphcore and saw the power consumption plateaus firsthand. Peter Vigil brought decades of DV experience and chose Normal because both sides of the problem, the tooling and the hardware, are being built under one roof. Brandon Birchall is working on diffusion acceleration from first principles, going bottom-up from unconventional physics and top-down from real workloads at the same time. As Peter Vigil reflects: "What makes Normal truly unique? Because we are also working on silicon, we are able to test our own verification EDA tools against the designs as we build them. And so we have this very nice closed loop where we can take feedback from the design work we're doing and feed that right into our tools." We're hiring across teams. Link in comments.

Thank you to Celesta Capital for hosting us at Deep Tech Week NYC for a standing room only for a conversation about the future of computing. Our co-founder Antonio Martinez and Business Operations Lead Sammer Richi spoke with Partner David Goldman about our recent $50M raise and the thesis behind Normal: AI and hardware are converging into a single design loop. To get there, we're building both AI for silicon engineering, and a new thermodynamic computing architecture that rethinks energy efficiency. Appreciate Celesta GPs Nicholas Brathwaite and Michael E Marks for the sharp breakdown on what we're seeing in the market now, and everyone who showed up!